efabless / raptor_soc_templateLinks
Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.
☆22Updated 6 years ago
Alternatives and similar repositories for raptor_soc_template
Users that are interested in raptor_soc_template are comparing it to the libraries listed below
Sorting:
- ☆16Updated 6 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆18Updated 11 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 7 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- ☆26Updated 4 years ago
- ☆26Updated 4 months ago
- Implementation of the PCIe physical layer☆57Updated 4 months ago
- DMA core compatible with AHB3-Lite☆10Updated 6 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆48Updated last year
- A 32 point radix-2 FFT module written in Verilog☆23Updated 5 years ago
- ☆20Updated 3 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- ☆21Updated 6 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Updated 4 years ago
- ☆14Updated 6 years ago
- Verification IP for Watchdog☆11Updated 4 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆19Updated 7 years ago
- Generic AXI master stub☆19Updated 11 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆15Updated 5 years ago
- ☆12Updated 10 years ago
- AXI Interconnect☆54Updated 4 years ago
- The memory model was leveraged from micron.☆24Updated 7 years ago
- UVM resource from github, run simulation use YASAsim flow☆31Updated 5 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆24Updated 5 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Updated 9 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆38Updated 8 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆35Updated 5 months ago
- ☆17Updated 10 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Updated 7 years ago
- A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…☆15Updated 7 years ago