efabless / raptor_soc_templateLinks
Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.
☆22Updated 6 years ago
Alternatives and similar repositories for raptor_soc_template
Users that are interested in raptor_soc_template are comparing it to the libraries listed below
Sorting:
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 7 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- ☆26Updated 4 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆35Updated last week
- ☆16Updated 6 years ago
- UVM resource from github, run simulation use YASAsim flow☆32Updated 5 years ago
- Implementation of the PCIe physical layer☆60Updated 6 months ago
- ☆22Updated 6 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Updated 5 years ago
- WISHBONE Interconnect☆11Updated 8 years ago
- ☆20Updated 3 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆19Updated 11 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆30Updated 3 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆25Updated 6 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- Generate UVM testbench framework template files with Python 3☆27Updated 6 years ago
- Verification AXI-4 bus standard using UVM and System Verilog☆15Updated 7 years ago
- - Designed a Nand Flash Controller, Flash Memory and Buffer (Design Target : Samsung K9F1G08R0A NAND Flash). - Implemented operations : …☆21Updated 7 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆55Updated 4 years ago
- A Verilog AMBA AHB Multilayer interconnect generator☆12Updated 8 years ago
- Generic AXI master stub☆19Updated 11 years ago
- DMA core compatible with AHB3-Lite☆10Updated 6 years ago
- 异步FIFO的内部实现☆25Updated 7 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆47Updated last year
- CORE-V MCU UVM Environment and Test Bench☆25Updated last year
- AXI Interconnect☆54Updated 4 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Updated 9 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆17Updated 2 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- Build an open source, extremely simple DMA.☆23Updated 6 years ago