efabless / raptor_soc_templateLinks
Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.
☆22Updated 5 years ago
Alternatives and similar repositories for raptor_soc_template
Users that are interested in raptor_soc_template are comparing it to the libraries listed below
Sorting:
- ☆16Updated 6 years ago
- ☆20Updated 2 years ago
- Implementation of the PCIe physical layer☆48Updated 2 months ago
- ☆26Updated 4 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Updated 4 years ago
- DMA core compatible with AHB3-Lite☆10Updated 6 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆34Updated 3 months ago
- UVM resource from github, run simulation use YASAsim flow☆30Updated 5 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆45Updated last year
- - Designed a Nand Flash Controller, Flash Memory and Buffer (Design Target : Samsung K9F1G08R0A NAND Flash). - Implemented operations : …☆21Updated 7 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆24Updated 5 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- ☆14Updated 6 years ago
- WISHBONE Interconnect☆11Updated 7 years ago
- To design test bench of the APB protocol☆17Updated 4 years ago
- ☆21Updated 5 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆15Updated 2 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆14Updated 5 years ago
- A Verilog AMBA AHB Multilayer interconnect generator☆12Updated 8 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆17Updated 11 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- AXI Interconnect☆52Updated 4 years ago
- Verification IP for UART protocol☆20Updated 5 years ago
- A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…☆15Updated 7 years ago
- Verification IP for Watchdog☆11Updated 4 years ago
- ☆21Updated 5 years ago
- It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.☆18Updated 5 years ago