charkster / spi_slave_verilogLinks
SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs
☆20Updated 6 years ago
Alternatives and similar repositories for spi_slave_verilog
Users that are interested in spi_slave_verilog are comparing it to the libraries listed below
Sorting:
- Verilog SPI master and slave☆62Updated 10 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68Updated 5 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆53Updated 2 years ago
- USB -> AXI Debug Bridge☆41Updated 4 years ago
- UART -> AXI Bridge☆69Updated 4 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆75Updated 5 years ago
- Interface Protocol in Verilog☆51Updated 6 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆97Updated 5 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆81Updated 3 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆78Updated 3 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆39Updated 4 years ago
- IEEE P1735 decryptor for VHDL☆39Updated 10 years ago
- SDRAM controller with AXI4 interface☆100Updated 6 years ago
- RTL Verilog library for various DSP modules☆93Updated 3 years ago
- ☆28Updated 4 years ago
- USB 2.0 Device IP Core☆73Updated 8 years ago
- ☆80Updated 3 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆76Updated 2 months ago
- Ethernet MAC 10/100 Mbps☆83Updated 6 years ago
- Verilog Ethernet Switch (layer 2)☆50Updated 2 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆32Updated 7 years ago
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆17Updated last month
- Implementation of the PCIe physical layer☆60Updated 6 months ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆63Updated 3 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆34Updated 5 years ago
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆132Updated 5 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆47Updated last year
- ☆38Updated 10 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆72Updated 8 months ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆42Updated 3 months ago