charkster / spi_slave_verilogLinks
SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs
☆17Updated 5 years ago
Alternatives and similar repositories for spi_slave_verilog
Users that are interested in spi_slave_verilog are comparing it to the libraries listed below
Sorting:
- UART -> AXI Bridge☆63Updated 4 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆50Updated last year
- USB -> AXI Debug Bridge☆39Updated 4 years ago
- Verilog SPI master and slave☆59Updated 9 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆74Updated 2 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆66Updated 5 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆66Updated 4 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆94Updated 5 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆79Updated 3 years ago
- IEEE P1735 decryptor for VHDL☆36Updated 10 years ago
- Interface Protocol in Verilog☆50Updated 6 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆45Updated last year
- SERDES-based TDC core for Spartan-6☆18Updated 13 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆30Updated last year
- ☆27Updated 4 years ago
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆60Updated 3 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆39Updated 2 weeks ago
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- A collection of phase locked loop (PLL) related projects☆111Updated last year
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆16Updated 3 years ago
- Verilog FT245 to AXI stream interface☆29Updated 7 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆65Updated 3 years ago
- ☆79Updated 3 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆39Updated 4 years ago
- Verilog module to transmit/receive to/from RGMII compatible ethernet PHY☆29Updated 2 years ago
- Video Stream Scaler☆40Updated 11 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆35Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆84Updated 6 years ago