this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.
☆19Jul 29, 2014Updated 11 years ago
Alternatives and similar repositories for ahb2apb
Users that are interested in ahb2apb are comparing it to the libraries listed below
Sorting:
- ☆10Aug 12, 2021Updated 4 years ago
- Generic AHB master stub☆12Jul 17, 2014Updated 11 years ago
- AHB-APB Bridge RTL Design☆15Apr 19, 2018Updated 7 years ago
- ☆38Aug 12, 2015Updated 10 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m …☆22Feb 25, 2019Updated 7 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆48May 10, 2024Updated last year
- Collection of IPs based on AMBA (AHB, APB, AXI) protocols☆19Feb 1, 2017Updated 9 years ago
- ☆12Nov 11, 2015Updated 10 years ago
- A simple spidergon network-on-chip with wormhole switching feature☆12Mar 22, 2021Updated 5 years ago
- CNN accelerator using NoC architecture☆18Dec 6, 2018Updated 7 years ago
- The source code of blog☆14Dec 12, 2021Updated 4 years ago
- Rewrite XuanTieC910 with chisel3☆12Jul 1, 2022Updated 3 years ago
- ☆21Sep 26, 2025Updated 5 months ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆17Jan 25, 2022Updated 4 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆106Jul 2, 2023Updated 2 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- Various low power labs using sky130☆13Sep 3, 2021Updated 4 years ago
- An uvm verification env for ahb2apb bridge☆57Apr 9, 2021Updated 4 years ago
- ☆20Nov 18, 2022Updated 3 years ago
- ☆11Mar 10, 2023Updated 3 years ago
- UVM AHB VIP☆96Sep 13, 2025Updated 6 months ago
- AHB Bus lite v3.0☆17Aug 7, 2019Updated 6 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Oct 9, 2019Updated 6 years ago
- ☆14Jun 30, 2019Updated 6 years ago
- ☆10Oct 18, 2024Updated last year
- A Direct Memory Access Controller (DMAC) with AHB-lite bus interface☆17Oct 6, 2024Updated last year
- Extremely basic CortexM0 SoC based on ARM DesignStart Eval☆28Oct 8, 2018Updated 7 years ago
- ☆20Aug 22, 2022Updated 3 years ago
- Quad cluster of RISC-V cores with peripherals and local memory☆24Feb 3, 2022Updated 4 years ago
- Pan's 1st Gen RISC-V SoC, contains a 12T multicycle RISC-V32ia core, with an EMIF-like simple bus☆16Oct 21, 2020Updated 5 years ago
- ☆18Apr 5, 2015Updated 10 years ago
- This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented wi…☆20Sep 3, 2019Updated 6 years ago
- Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.☆17Dec 19, 2022Updated 3 years ago
- ☆16Apr 21, 2019Updated 6 years ago
- FPGA-CNN Application for fruit detection based on Logos-PGL22G Board☆14Aug 24, 2022Updated 3 years ago
- AHB/APB SRAM Inf, VCS&Verdi Sim.☆16Jun 20, 2022Updated 3 years ago
- ☆19Aug 11, 2022Updated 3 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68May 8, 2020Updated 5 years ago
- Distributed arithmetic (DA) is another way of implementing a dot product where one of the arrays has constant elements. The DA can be eff…☆16Aug 26, 2021Updated 4 years ago