A SPI Master IP written in verilog which is then used to output characters entered on a keypad to a serial LCD screen
☆20Dec 5, 2014Updated 11 years ago
Alternatives and similar repositories for Verilog-SPI-Master
Users that are interested in Verilog-SPI-Master are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆72May 8, 2020Updated 6 years ago
- I2C Master Verilog module☆38Jun 1, 2025Updated last year
- General Purpose IO with APB4 interface☆17May 10, 2024Updated 2 years ago
- Verilog SPI master and slave☆63Jan 4, 2016Updated 10 years ago
- PCB Schematics for the Nabu PC☆13May 3, 2024Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs☆21Dec 15, 2019Updated 6 years ago
- ☆18Apr 5, 2015Updated 11 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆36Mar 21, 2020Updated 6 years ago
- Verilog implementation of an SPI slave interface. Intially targetted for Atlys devkit (Xilinx Spartan-6) controlled by TotalPhase Cheetah…☆42Jan 8, 2025Updated last year
- FPGA controller for SSD1306 OLED module on SPI. Optimised for GOWIN FPGA☆17Oct 11, 2018Updated 8 years ago
- An i2c master controller implemented in Verilog☆37Jul 26, 2017Updated 9 years ago
- A simple 8 bit UART implementation in Verilog, with tests and timing diagrams☆42Oct 13, 2026Updated 3 weeks ago
- NABU Network Adaptor, Windows, Mono (Mac, Linux, Pi, etc), and Console based on the .NET framework.☆21Mar 7, 2024Updated 2 years ago
- SPI core☆12Jul 17, 2014Updated 12 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- framework for a simple user space for lk☆26Sep 7, 2026Updated 2 months ago
- A hardware implementation of the Consolite game console written in Verilog.☆11Jun 9, 2016Updated 10 years ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆34Apr 29, 2024Updated 2 years ago
- Small py script to extract CLOVERX64.efi from an install package and copy it to a target drive's EFI partition.☆13Nov 16, 2025Updated 11 months ago
- Design and simulate a simplified ARM single-cycle processor using SystemVerilog.☆10Sep 13, 2019Updated 7 years ago
- This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.☆12Sep 6, 2023Updated 3 years ago
- A simple spidergon network-on-chip with wormhole switching feature☆13Mar 22, 2021Updated 5 years ago
- SymbiFlow Website Source☆12Apr 7, 2022Updated 4 years ago
- ☆17Aug 18, 2020Updated 6 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- A simple flutter application using dart ffi and C++ class☆12Dec 21, 2020Updated 5 years ago
- ☆14Nov 13, 2022Updated 3 years ago
- Self-driving Model Car with RPi☆10Nov 27, 2020Updated 5 years ago
- Personal mirror for adv_debug_sys☆11Aug 23, 2011Updated 15 years ago
- GPIO IP core from opencores.☆12May 22, 2014Updated 12 years ago
- Hardware-accelerated sorting algorithm☆16May 4, 2020Updated 6 years ago
- Tiny Tapeout 06☆19Nov 15, 2025Updated 11 months ago
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago
- Controller for i2c EEPROM chip in Verilog for Mojo FPGA board☆28Mar 9, 2016Updated 10 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- PID controller with FPGA hardware☆21Oct 5, 2019Updated 7 years ago
- 单周期CPU设计与实现☆15Dec 30, 2022Updated 3 years ago
- WM8731 Audio CODEC using Verilog (DE2-115)☆12Jul 28, 2019Updated 7 years ago
- JESD204b modules in VHDL☆31Apr 18, 2019Updated 7 years ago
- Cryptography accelerator ASIC (for AES128/AES256 and SHA256) using Skywater 130nm process node (build-environment repo).☆11Jan 13, 2021Updated 5 years ago
- ☆13Mar 10, 2023Updated 3 years ago