design and verification of asynchronous circuits
☆48Feb 27, 2026Updated 2 months ago
Alternatives and similar repositories for loom
Users that are interested in loom are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A Rocket-based RISC-V superscalar in-order core☆38Mar 11, 2026Updated last month
- 21st century electronic design automation tools, written in Rust.☆36Apr 16, 2026Updated last week
- Easy SMT solver interaction☆34Feb 3, 2026Updated 2 months ago
- A fork of Yosys that integrates the CellIFT pass☆13Apr 21, 2026Updated last week
- Characterizer☆34Nov 19, 2025Updated 5 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Analyze experimental data with Programming by Navigation☆17Updated this week
- Parametrized RTL benchmark suite☆26Feb 6, 2026Updated 2 months ago
- Rust proof-of-concept for GPU waveform rendering☆13Jul 22, 2020Updated 5 years ago
- RTLCheck☆25Oct 9, 2018Updated 7 years ago
- Primitives for GF180MCU provided by GlobalFoundries.☆56Aug 28, 2023Updated 2 years ago
- VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation deb…☆37Nov 6, 2025Updated 5 months ago
- ☆29Mar 31, 2025Updated last year
- UCSD Sizer for leakage/dynamic power recovery, timing recovery☆18Mar 5, 2019Updated 7 years ago
- Template Verilator project for beginners☆13Feb 2, 2023Updated 3 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Sep 20, 2023Updated 2 years ago
- ☆18Jul 12, 2024Updated last year
- ☆15Jan 25, 2026Updated 3 months ago
- [MIGRATED to https://codeberg.org/prjunnamed/prjunnamed] End-to-end synthesis and P&R toolchain☆94Mar 12, 2026Updated last month
- An open silicon CHERIoT Ibex microcontroller chip☆18May 23, 2025Updated 11 months ago
- Exploring gate level simulation☆58Mar 27, 2026Updated last month
- high-performance RTL simulator☆191Jun 19, 2024Updated last year
- VS Code based debugger for hardware designs in Amaranth or Verilog☆39Dec 3, 2024Updated last year
- Logic circuit analysis and optimization☆48Feb 2, 2026Updated 2 months ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Open-source repository for a standard-cell library characterizer using complete open-source tools☆53Updated this week
- Description of Apple's LEAP ISA☆16Nov 21, 2022Updated 3 years ago
- Examples and design pattern for VHDL verification☆15Apr 10, 2016Updated 10 years ago
- Interpreter and compiler for the ISA specification language "Architecture Specification Language" (ASL)☆28Updated this week
- ☆25Jun 23, 2024Updated last year
- UB-aware interpreter for LLVM debugging☆48Mar 26, 2026Updated last month
- Structural Netlist API (and more) for EDA post synthesis flow development☆136Updated this week
- Dual-Core Out-of-Order MIPS CPU Design☆23May 8, 2025Updated 11 months ago
- Open-source PDK version manager☆47Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A tool for synthesizing Verilog programs☆113Aug 25, 2025Updated 8 months ago
- ☆13Feb 3, 2025Updated last year
- easter egg is a flexible, high-performance e-graph library with support of multiple additional assumptions at once☆13Mar 27, 2025Updated last year
- Code repository for Coppelia tool☆24Nov 12, 2020Updated 5 years ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆43Mar 7, 2024Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Jun 28, 2025Updated 10 months ago
- SimCommand is a library for writing high-performance RTL testbenches with simulation threads in Scala using chiseltest.☆14Aug 30, 2023Updated 2 years ago