broccolimicro / loomLinks
design and verification of asynchronous circuits
☆40Updated last week
Alternatives and similar repositories for loom
Users that are interested in loom are comparing it to the libraries listed below
Sorting:
- A SystemVerilog language server based on the Slang parser and library.☆40Updated last week
- A configurable SRAM generator☆56Updated last month
- An automatic clock gating utility☆50Updated 5 months ago
- 21st century electronic design automation tools, written in Rust.☆31Updated last week
- ☆32Updated 9 months ago
- Hardware generator debugger☆76Updated last year
- ☆38Updated 3 years ago
- Mutation Cover with Yosys (MCY)☆87Updated this week
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- ☆19Updated last year
- Gate-level visualization generator for SKY130-based chip designs.☆21Updated 4 years ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆115Updated 4 months ago
- ☆54Updated 6 months ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 5 years ago
- Equivalence checking with Yosys☆47Updated this week
- A fault-injection framework using Chisel and FIRRTL☆36Updated 3 weeks ago
- AXI Formal Verification IP☆20Updated 4 years ago
- ☆56Updated 3 years ago
- A SystemVerilog source file pickler.☆60Updated 11 months ago
- Logic circuit analysis and optimization☆42Updated last month
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 3 months ago
- CMake based hardware build system☆31Updated this week
- Fast PnR toolchain for CGRA☆18Updated last year
- Open source RTL simulation acceleration on commodity hardware☆29Updated 2 years ago
- YosysHQ SVA AXI Properties☆42Updated 2 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆19Updated 3 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- RTLMeter benchmark suite☆28Updated this week
- Hardware abstraction library☆39Updated this week
- Supplemental technology files for ASAP7 PDK with Synopsys design flow☆18Updated 2 years ago