Alternatives and similar repositories for loom

Users that are interested in loom are comparing it to the libraries listed below

• AUCOHL / Lighter
  An automatic clock gating utility
  ☆51Updated 9 months ago
• pulp-platform / svase
  ☆33Updated last year
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• Kuree / hgdb
  Hardware generator debugger
  ☆77Updated last year
• rahulk29 / sram22
  A configurable SRAM generator
  ☆57Updated 5 months ago
• pulp-platform / ELAU
  ☆20Updated last year
• dh73 / A_Formal_Tale_Chapter_I_AMBA
  AXI Formal Verification IP
  ☆22Updated 4 years ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆55Updated 2 weeks ago
• Coloquinte / quaigh
  Logic circuit analysis and optimization
  ☆45Updated 5 months ago
• ucb-substrate / substrate2
  21st century electronic design automation tools, written in Rust.
  ☆33Updated last week
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆35Updated 5 years ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆90Updated 2 weeks ago
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆120Updated 8 months ago
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆21Updated 4 years ago
• antmicro / sv-bugpoint
  ☆34Updated 3 weeks ago
• tdene / synth_opt_adders
  Prefix tree adder space exploration library
  ☆56Updated last year
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆44Updated 2 years ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• chipsalliance / fpga-interchange-schema
  ☆59Updated 3 years ago
• snishizawa / asap7_snps
  Supplemental technology files for ASAP7 PDK with Synopsys design flow
  ☆21Updated 3 years ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆43Updated 2 years ago
• Kuree / cgra_pnr
  Fast PnR toolchain for CGRA
  ☆18Updated last year
• Kuree / kratos
  Debuggable hardware generator
  ☆70Updated 2 years ago
• HEP-SoC / SoCMake
  CMake based hardware build system
  ☆35Updated this week
• antmicro / verilator-uvm-example
  Example of how to use UVM with Verilator
  ☆33Updated last month
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆50Updated last week
• phanrahan / mantle
  mantle library
  ☆44Updated 3 years ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated 4 months ago
• tdb-alcorn / chisel-formal
  ☆24Updated 4 years ago