broccolimicro / loomLinks
design and verification of asynchronous circuits
☆41Updated last week
Alternatives and similar repositories for loom
Users that are interested in loom are comparing it to the libraries listed below
Sorting:
- An automatic clock gating utility☆51Updated 7 months ago
- 21st century electronic design automation tools, written in Rust.☆32Updated this week
- ☆33Updated 10 months ago
- ☆38Updated 3 years ago
- ☆57Updated 3 years ago
- A configurable SRAM generator☆57Updated 3 months ago
- ☆20Updated last year
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆43Updated 2 years ago
- A SystemVerilog language server based on the Slang library.☆64Updated this week
- Supplemental technology files for ASAP7 PDK with Synopsys design flow☆19Updated 2 years ago
- Equivalence checking with Yosys☆51Updated last week
- Hardware generator debugger☆77Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 4 months ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 2 months ago
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 5 years ago
- Mutation Cover with Yosys (MCY)☆88Updated last week
- An open source PDK using TIGFET 10nm devices.☆54Updated 2 years ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆116Updated 6 months ago
- RTLMeter benchmark suite☆28Updated 3 weeks ago
- Library of open source Process Design Kits (PDKs)☆59Updated 2 weeks ago
- AXI Formal Verification IP☆20Updated 4 years ago
- GL0AM GPU Accelerated Gate Level Logic Simulator☆28Updated 3 months ago
- Logic circuit analysis and optimization☆42Updated 3 months ago
- Hardware abstraction library☆42Updated 3 weeks ago
- ☆23Updated 4 years ago
- Debuggable hardware generator☆70Updated 2 years ago
- Fast PnR toolchain for CGRA☆18Updated last year
- Using e-graphs to synthesize netlists from boolean logic.☆14Updated 2 years ago
- ☆58Updated 7 months ago