Alternatives and similar repositories for loom

Users that are interested in loom are comparing it to the libraries listed below

• pulp-platform / svase
  ☆32Updated 7 months ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆50Updated 3 months ago
• pulp-platform / ELAU
  ☆19Updated last year
• rahulk29 / sram22
  A configurable SRAM generator
  ☆53Updated last month
• ucb-substrate / substrate2
  21st century electronic design automation tools, written in Rust.
  ☆31Updated last week
• Kuree / hgdb
  Hardware generator debugger
  ☆75Updated last year
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆45Updated this week
• snishizawa / asap7_snps
  Supplemental technology files for ASAP7 PDK with Synopsys design flow
  ☆16Updated 2 years ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆34Updated 4 years ago
• dh73 / A_Formal_Tale_Chapter_I_AMBA
  AXI Formal Verification IP
  ☆20Updated 4 years ago
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆20Updated 4 years ago
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆85Updated last month
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆49Updated this week
• siliconcompiler / lambdalib
  Hardware abstraction library
  ☆36Updated this week
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆37Updated 3 months ago
• Coloquinte / quaigh
  Logic circuit analysis and optimization
  ☆43Updated last month
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆42Updated 2 years ago
• pulp-platform / cheshire-ihp130-o
  ☆47Updated 4 months ago
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆110Updated 2 months ago
• IntelLabs / pycaliper
  PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…
  ☆22Updated last month
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• projectapheleia / avl
  Apheleia Verification Library. A Python based HDL verification library sitting on top of cocotb
  ☆29Updated this week
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆42Updated 2 years ago
• chipsalliance / fpga-interchange-schema
  ☆56Updated 3 years ago
• HEP-SoC / SoCMake
  CMake based hardware build system
  ☆29Updated 2 weeks ago
• verilator / rtlmeter
  RTLMeter benchmark suite
  ☆20Updated last month
• antmicro / sv-bugpoint
  ☆28Updated this week
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆27Updated 3 years ago
• lip6 / coriolis
  Coriolis VLSI EDA Tool (LIP6)
  ☆69Updated last week