heyfey / sv-pathfinderLinks
VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation debug
☆34Updated 2 months ago
Alternatives and similar repositories for sv-pathfinder
Users that are interested in sv-pathfinder are comparing it to the libraries listed below
Sorting:
- SpiceBind – spice inside HDL simulator☆56Updated 6 months ago
- Characterizer☆30Updated last month
- Fabric generator and CAD tools graphical frontend☆17Updated 5 months ago
- Making cocotb testbenches that bit easier☆36Updated 2 months ago
- An open-source HDL register code generator fast enough to run in real time.☆81Updated last month
- ☆33Updated last year
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 3 years ago
- IP Core Library - Published and maintained by the Open Source VHDL Group☆49Updated last month
- submission repository for efabless mpw6 shuttle☆31Updated 2 years ago
- SystemVerilog Linter based on pyslang☆31Updated 8 months ago
- ☆42Updated 3 years ago
- Summer School Week 1 & 2 repo☆11Updated 3 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆77Updated 5 months ago
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆50Updated 10 months ago
- UART cocotb module☆11Updated 4 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆32Updated last year
- Python Tool for UVM Testbench Generation☆55Updated last year
- This project contains Verilog designs and a PCB for the implementation of CSI-2 camera interface to HDMI bridge on a Gatemate FPGA from C…☆19Updated 5 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆54Updated last week
- An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders☆21Updated last week
- Python interface for cross-calling with HDL☆45Updated last week
- Open-source PDK version manager☆35Updated last month
- Open Source Verification Bundle for VHDL and System Verilog☆48Updated 2 years ago
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆48Updated last week
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments☆69Updated 3 months ago
- Quick'n'dirty FuseSoC+cocotb example☆19Updated last year
- Open source ISS and logic RISC-V 32 bit project☆60Updated last month
- 55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.☆153Updated 2 weeks ago
- An automatic clock gating utility☆51Updated 9 months ago
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆51Updated last week