VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation debug
☆37Nov 6, 2025Updated 4 months ago
Alternatives and similar repositories for sv-pathfinder
Users that are interested in sv-pathfinder are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Library of FPGA architectures☆31Mar 9, 2026Updated 2 weeks ago
- Debug waveforms with GDB☆29Nov 12, 2025Updated 4 months ago
- Fabric generator and CAD tools graphical frontend☆18Aug 5, 2025Updated 7 months ago
- Yosys plugin for logic locking and supply-chain security☆23Apr 5, 2025Updated 11 months ago
- Python interface for cross-calling with HDL☆49Mar 14, 2026Updated last week
- NordVPN Threat Protection Pro™ • AdTake your cybersecurity to the next level. Block phishing, malware, trackers, and ads. Lightweight app that works with all browsers.
- 10GbE XGMII TCP/IPv4 packet generator in C, co-simulating with Verilog, SystemVerilog and VHDL☆26Jan 28, 2025Updated last year
- Template Verilator project for beginners☆13Feb 2, 2023Updated 3 years ago
- A Rocket-based RISC-V superscalar in-order core☆38Mar 11, 2026Updated 2 weeks ago
- SystemVerilog file list pruner☆17Mar 2, 2026Updated 3 weeks ago
- Coverview☆28Jan 29, 2026Updated last month
- 55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.☆182Feb 28, 2026Updated last month
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆118Mar 20, 2026Updated last week
- Hardware transactions library for Amaranth☆26Mar 9, 2026Updated 2 weeks ago
- An open silicon CHERIoT Ibex microcontroller chip☆18May 23, 2025Updated 10 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- A Python package for generating HDL wrappers and top modules for HDL sources☆64Updated this week
- Native Rust implementation of the FST waveform format from GTKWave.☆13Mar 12, 2026Updated 2 weeks ago
- Making cocotb testbenches that bit easier☆38Feb 28, 2026Updated 3 weeks ago
- Summer School Week 1 & 2 repo☆12Jul 1, 2022Updated 3 years ago
- Filelist generator☆20Updated this week
- A SytemVerilog implementation of Cyclic Redundancy Check runs at up to Terabits per second☆19Oct 23, 2023Updated 2 years ago
- design and verification of asynchronous circuits☆48Feb 27, 2026Updated last month
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆85Jan 28, 2026Updated last month
- System on Chip toolkit for Amaranth HDL☆100Mar 3, 2026Updated 3 weeks ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- VLSI placement and routing tool☆15Dec 20, 2025Updated 3 months ago
- LunaPnR is a place and router for integrated circuits☆47Feb 11, 2026Updated last month
- Administrative repository for the Integrated Matrix Extension Task Group☆34Dec 15, 2025Updated 3 months ago
- Parse FSDB waveform files☆22Nov 4, 2025Updated 4 months ago
- APB UVC ported to Verilator☆11Nov 19, 2023Updated 2 years ago
- Control and status register code generator toolchain☆181Feb 27, 2026Updated last month
- SPI RAM Emulation on Pico☆37Jul 30, 2023Updated 2 years ago
- cocotb extension for nMigen☆17Feb 26, 2022Updated 4 years ago
- Parametrized RTL benchmark suite☆25Feb 6, 2026Updated last month
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Simple UVM environment for experimenting with Verilator.☆38Updated this week
- A configurable and approachable tool for FPGA debugging and rapid prototyping.☆146Mar 17, 2026Updated last week
- Open source RTL simulation acceleration on commodity hardware☆34Apr 13, 2023Updated 2 years ago
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆27Feb 2, 2026Updated last month
- ☆38Mar 17, 2026Updated last week
- An open-source HDL register code generator fast enough to run in real time.☆84Updated this week
- Library of open source PDKs☆68Updated this week