Alternatives and similar repositories for riscv-hpmcounters

Users that are interested in riscv-hpmcounters are comparing it to the libraries listed below

• hanhwi / SimPoint
  ☆17Updated 3 years ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆102Updated last week
• comparch-security / cache-model
  A behavioural cache model for analysing the cache behaviour under side-channel attack.
  ☆26Updated 3 months ago
• miaochenlu / Gem5_tutorials
  ☆20Updated 4 months ago
• NetTLP / adapter
  An FPGA-based NetTLP adapter
  ☆26Updated 5 years ago
• efeslab / moesi-prime
  ☆15Updated 2 years ago
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆42Updated last year
• riscv / riscv-control-transfer-records
  This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…
  ☆23Updated 7 months ago
• OpenXiangShan / xfuzz
  Fuzzing General-Purpose Hardware Designs with Software Fuzzers
  ☆21Updated 3 weeks ago
• cnrv / RVWC2021-slides
  第一届 RISC-V 中国峰会的幻灯片等资料存放
  ☆38Updated 2 years ago
• NetTLP / libtlp
  A library for PCIe Transaction Layer
  ☆60Updated 3 years ago
• zero-day-labs / riscv-iommu-demo
  RISC-V IOMMU Demo (Linux & Bao)
  ☆23Updated last year
• comsec-group / encarsia
  ☆23Updated 6 months ago
• comparch-security / chipyard-random-llc
  A Rocket-Chip with a Dynamically Randomized LLC
  ☆13Updated last year
• riscv / riscv-smmtt
  This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…
  ☆60Updated this week
• esl-epfl / gem5-X
  The gem5-X open source framework (based on the gem5 simulator)
  ☆42Updated 2 years ago
• aakahlow / gem5Valid_Haswell
  ☆20Updated 5 years ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆61Updated 3 years ago
• ccelio / Speckle
  A wrapper for the SPEC CPU2006 benchmark suite.
  ☆89Updated 4 years ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 10 months ago
• efeslab / lapidary
  Creating beautiful gem5 simulations
  ☆49Updated 4 years ago
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago
• shinezyy / gem5-official-old
  ☆20Updated 4 years ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• hadibrais / archsim
  A survey on architectural simulators focused on CPU caches.
  ☆16Updated 5 years ago
• ucb-bar / libgloss-htif
  A libgloss replacement for RISC-V that supports HTIF
  ☆38Updated last year
• parsa-epfl / qflex
  Quick & Flexible Rack-Scale Computer Architecture Simulator
  ☆50Updated this week
• epfl-vlsc / parendi
  Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU
  ☆23Updated last year
• nus-comparch / looppoint
  Sampled simulation of multi-threaded applications using LoopPoint methodology
  ☆20Updated 2 months ago
• nbdd0121 / TLBSim
  Fast TLB simulator for RISC-V systems
  ☆14Updated 6 years ago