Alternatives and similar repositories for sunburst-chip

Users that are interested in sunburst-chip are comparing it to the libraries listed below

• PeterMonsson / sv_waveterm
  ☆10Updated 2 years ago
• RoaLogic / ahb3lite_pkg
  Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
  ☆18Updated last year
• pulp-platform / svase
  ☆33Updated last year
• AsFigo / apb_uvc_verilator
  APB UVC ported to Verilator
  ☆11Updated 2 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 7 months ago
• accellera-official / PySysC
  Public repository for PySysC, (From SC Common Practices Subgroup)
  ☆54Updated 2 years ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 9 months ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆56Updated this week
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆60Updated 2 weeks ago
• esa-tu-darmstadt / SCAIE-V-2.0
  Scalable Interface for RISC-V ISA Extensions
  ☆23Updated this week
• pulp-platform / axi_llc
  ☆33Updated 2 months ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆42Updated 5 years ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆34Updated 2 years ago
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆48Updated last month
• chipsalliance / caliptra-ss
  HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
  ☆36Updated this week
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆43Updated 3 years ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆26Updated 3 months ago
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆18Updated 2 years ago
• amichai-bd / riscv-multi-core-lotr
  RISCV core RV32I/E.4 threads in a ring architecture
  ☆33Updated 2 years ago
• wallento / cocotbext-uart
  UART cocotb module
  ☆11Updated 4 years ago
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆33Updated last year
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆36Updated last year
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆19Updated last year
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆44Updated 2 years ago
• embecosm / ri5cy
  The PULP RI5CY core modified for Verilator modeling and as a GDB server.
  ☆26Updated 7 years ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆48Updated 4 years ago
• habibagamal / SoC_Automation
  SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …
  ☆39Updated 5 years ago
• rggen / rggen-sv-rtl
  Common SystemVerilog RTL modules for RgGen
  ☆16Updated this week
• openhwgroup / cvw-arch-verif
  The purpose of the repo is to support CORE-V Wally architectural verification
  ☆17Updated 2 months ago
• mohamed / fsm2sv
  SystemVerilog FSM generator
  ☆33Updated last year