An open silicon CHERIoT Ibex microcontroller chip
☆18May 23, 2025Updated 9 months ago
Alternatives and similar repositories for sunburst-chip
Users that are interested in sunburst-chip are comparing it to the libraries listed below
Sorting:
- Design files and associated documentation for Sonata PCB, part of the Sunburst Project☆20Apr 1, 2025Updated 11 months ago
- Open-source implementations of reference Physical True Random Number Generators (TRNG or PTRNG) based on ring oscillators.☆15Oct 15, 2025Updated 5 months ago
- UVM components for DSP tasks (MODulation/DEModulation)☆14Mar 2, 2022Updated 4 years ago
- ☆23Mar 12, 2026Updated last week
- A Rocket-based RISC-V superscalar in-order core☆38Mar 11, 2026Updated last week
- Template Verilator project for beginners☆13Feb 2, 2023Updated 3 years ago
- Labs for the Ibex Demo System☆17Nov 18, 2023Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Jun 28, 2025Updated 8 months ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Feb 23, 2026Updated 3 weeks ago
- ☆10Nov 2, 2023Updated 2 years ago
- Administrative repository for the Integrated Matrix Extension Task Group☆34Dec 15, 2025Updated 3 months ago
- RISC-V Nox core☆71Jul 22, 2025Updated 7 months ago
- cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.☆125Mar 6, 2026Updated 2 weeks ago
- Online documentation can be found at https://minres.github.io/SCViewer/☆21Feb 11, 2024Updated 2 years ago
- A light-weight hardware oriented synchronous stream cipher.☆12Mar 19, 2022Updated 4 years ago
- Build infrastructure for class-wide tapeout for 18-224/624 Intro to Open Source Chip Design, Spring 2023☆20Aug 10, 2023Updated 2 years ago
- VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation deb…☆37Nov 6, 2025Updated 4 months ago
- Trying to learn Wishbone by implementing few master/slave devices☆13Jan 7, 2019Updated 7 years ago
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆38Dec 23, 2021Updated 4 years ago
- 10GbE XGMII TCP/IPv4 packet generator in C, co-simulating with Verilog, SystemVerilog and VHDL☆26Jan 28, 2025Updated last year
- ☆26Jul 27, 2017Updated 8 years ago
- Rust API for the STM32F0 micro controller☆18Aug 7, 2018Updated 7 years ago
- Open FPGA Modules☆24Oct 8, 2024Updated last year
- design and verification of asynchronous circuits☆44Feb 27, 2026Updated 3 weeks ago
- A copy of Atari's coin-op assembler and tools, as well as coin-op Centipede☆22Jan 27, 2024Updated 2 years ago
- Discover and enumerate all PLC devices and applications via a snap☆13May 28, 2018Updated 7 years ago
- ☆38Updated this week
- HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.☆39Updated this week
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆69Dec 1, 2022Updated 3 years ago
- Port of MIT's xv6 OS to 32 bit RISC V☆12Feb 12, 2023Updated 3 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆50Feb 11, 2026Updated last month
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆32Oct 15, 2024Updated last year
- Website for the OpenROAD tutorial held at the MICRO 2022 conference☆35Oct 6, 2022Updated 3 years ago
- smallest z80 disassembler in the world☆12Jan 28, 2023Updated 3 years ago
- CVA6 SDK containing RISC-V tools and Buildroot☆80Jan 28, 2026Updated last month
- OpenCCA: An Open Framework to Enable Arm CCA Research☆21Sep 10, 2025Updated 6 months ago
- BUSted!!! Microarchitectural Side-Channel Attacks on the MCU Bus Interconnect☆11May 21, 2024Updated last year
- microKanren sagittarius/larceny☆11Jun 13, 2015Updated 10 years ago
- Provide user-defined initialization semantics for arithmetic types.☆12Aug 26, 2018Updated 7 years ago