Chisel3 implementation of IEEE-754 compliant floating point data type (logic & representation)
☆11Dec 16, 2019Updated 6 years ago
Alternatives and similar repositories for Chisel3-Float-Type
Users that are interested in Chisel3-Float-Type are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Floating point modules for CHISEL☆32Nov 2, 2014Updated 11 years ago
- Chisel Project for Integrating RTL code into SDAccel☆17Jan 12, 2018Updated 8 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Apr 6, 2020Updated 6 years ago
- ☆14Apr 30, 2022Updated 4 years ago
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance☆12May 3, 2024Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs, with error detection capabili…☆14Aug 28, 2025Updated 8 months ago
- Repository containing the DSP gateware cores☆14Mar 9, 2026Updated last month
- RocketChip RoCC Accelerator template (Risc-V, Chisel )(加速器开发项目框架)☆15Sep 5, 2019Updated 6 years ago
- Verilog Examples and WebFPGA Standard Library☆11Nov 25, 2019Updated 6 years ago
- ☆18Sep 25, 2025Updated 7 months ago
- Approximate arithmetic circuits for FPGAs☆13Feb 19, 2020Updated 6 years ago
- Kernel Density Estimation: accelerated, multi-dimensional, and adaptive bandwidth☆14Aug 17, 2023Updated 2 years ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆28Jul 4, 2019Updated 6 years ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆51Oct 31, 2025Updated 6 months ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Cross compile FPGA tools☆21Jan 4, 2021Updated 5 years ago
- Deep learning library based on the gcForest algorithm☆12Dec 26, 2018Updated 7 years ago
- A library of verilog and vhdl modules☆15Nov 13, 2018Updated 7 years ago
- ☆22Oct 24, 2020Updated 5 years ago
- Sketches for DesignLab☆16Sep 10, 2017Updated 8 years ago
- A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…☆18Mar 5, 2018Updated 8 years ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆26Nov 15, 2021Updated 4 years ago
- BU-maintained version of the Jailhouse partitioning hypervisor with real-time features☆16Feb 28, 2021Updated 5 years ago
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆21Nov 2, 2025Updated 6 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A Rocket-based RISC-V superscalar in-order core☆38Mar 11, 2026Updated last month
- ☆19Aug 30, 2020Updated 5 years ago
- general-cores☆21Jul 16, 2025Updated 9 months ago
- AXI X-Bar☆19Apr 8, 2020Updated 6 years ago
- Userbot to log deleted and edited messages on Telegram☆19Feb 28, 2024Updated 2 years ago
- An automated HDC platform☆11Mar 16, 2026Updated last month
- CNN accelerator☆29Jun 11, 2017Updated 8 years ago
- RISC-V soft-core PEs for TaPaSCo☆23Jan 30, 2026Updated 3 months ago
- Implementation of a Systolic Array based sorting engine on an FPGA using Verilog☆11May 11, 2017Updated 8 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆13Feb 13, 2021Updated 5 years ago
- High-performance Spiking Neural Networks Library Written From Scratch with C++ and Python Interfaces.☆30Oct 11, 2025Updated 6 months ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Oct 9, 2019Updated 6 years ago
- EDA Tools: Xilinx ISE 14.7 Dockerfile☆21Jun 20, 2022Updated 3 years ago
- Revision Control Labs and Materials☆26Jan 23, 2018Updated 8 years ago
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆31Sep 22, 2018Updated 7 years ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆65Mar 21, 2023Updated 3 years ago