denishoornaert / Chisel3-Float-Type
Chisel3 implementation of IEEE-754 compliant floating point data type (logic & representation)
☆12Updated 5 years ago
Alternatives and similar repositories for Chisel3-Float-Type:
Users that are interested in Chisel3-Float-Type are comparing it to the libraries listed below
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 2 years ago
- Network on Chip for MPSoC☆25Updated 3 weeks ago
- Development of a Network on Chip Simulation using SystemC.☆31Updated 7 years ago
- Ratatoskr NoC Simulator☆22Updated 3 years ago
- ☆24Updated 5 years ago
- ☆11Updated 10 months ago
- TileLink Uncached Lightweight (TL-UL) implementation on Chisel.☆20Updated 4 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆32Updated 4 years ago
- Approximate arithmetic circuits for FPGAs☆11Updated 4 years ago
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 7 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆20Updated 3 weeks ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆62Updated 4 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- Reconfigurable Binary Engine☆15Updated 3 years ago
- RISC-V ISA based 32-bit processor written in HLS☆17Updated 5 years ago
- ☆42Updated 3 years ago
- Platform Level Interrupt Controller☆35Updated 8 months ago
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆11Updated 3 weeks ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆28Updated 3 weeks ago
- The source code that empowers OpenROAD Cloud☆12Updated 4 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆48Updated this week
- DSP WishBone Compatible Cores☆13Updated 10 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆28Updated 6 months ago
- DUTH RISC-V Superscalar Microprocessor☆29Updated 2 months ago