Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-mapped L1 Data Cache, and a 4-way set-associative L2 Victim Cache with a fully-associative 8-entry Victim Buffer. Also has a tournament branch predictor (global and local predictors) and a set-associative BTB.
☆14Dec 23, 2022Updated 3 years ago
Alternatives and similar repositories for RISCVPipelinedProcessor
Users that are interested in RISCVPipelinedProcessor are comparing it to the libraries listed below
Sorting:
- Write a CPU from scratch! (5-stage pipeline & 2-way-cache)☆20Jul 18, 2019Updated 6 years ago
- 第四届全国大学生嵌入式比赛SoC☆11Apr 1, 2022Updated 3 years ago
- Generic AHB master stub☆12Jul 17, 2014Updated 11 years ago
- 简单的未优化的SRT除法器☆12Jun 16, 2024Updated last year
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆13Nov 12, 2025Updated 3 months ago
- NTU Computer Architecture 2021 - CPU with Single issue, L1-cache☆11Jan 24, 2022Updated 4 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆55May 10, 2021Updated 4 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆16Aug 18, 2022Updated 3 years ago
- ☆14Feb 24, 2025Updated last year
- ☆10Dec 15, 2023Updated 2 years ago
- 一个支持AXI总线、支持Cache、包括所有非浮点MIPS 1指令、支持例外的静态五级流水MIPS CPU☆11Oct 8, 2019Updated 6 years ago
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆26Aug 28, 2016Updated 9 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆18Feb 12, 2024Updated 2 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆17Sep 2, 2023Updated 2 years ago
- To design test bench of the APB protocol☆18Dec 30, 2020Updated 5 years ago
- ☆18Apr 5, 2015Updated 10 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆16Jun 24, 2020Updated 5 years ago
- verilog/FPGA hardware description for very simple GPU☆16Apr 9, 2019Updated 6 years ago
- Maven Silicon Project☆20Oct 13, 2018Updated 7 years ago
- verification of simple axi-based cache☆18May 14, 2019Updated 6 years ago
- EE577b-Course-Project☆19May 6, 2020Updated 5 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Jul 8, 2013Updated 12 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆25Nov 24, 2019Updated 6 years ago
- Template for project1 TPU☆23May 1, 2021Updated 4 years ago
- Dual-core RISC-V SoC with JTAG, atomics, SDRAM☆25Jan 1, 2022Updated 4 years ago
- CPU Design Based on RISCV ISA☆130Jun 14, 2024Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆20Feb 4, 2026Updated 3 weeks ago
- General Purpose AXI Direct Memory Access☆62May 12, 2024Updated last year
- The memory model was leveraged from micron.☆28Mar 24, 2018Updated 7 years ago
- ☆27May 11, 2021Updated 4 years ago
- A Rocket-based RISC-V superscalar in-order core☆38Updated this week
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆32Aug 28, 2023Updated 2 years ago
- Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…☆68Aug 10, 2024Updated last year
- ☆77Feb 4, 2021Updated 5 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆14Mar 26, 2024Updated last year
- Functional Verification of Physical Layer of PCI Express Gen5.0 Graduation Project Using UVM☆25Jul 17, 2025Updated 7 months ago
- Pipelined FFT/IFFT 256 points processor☆10Jul 17, 2014Updated 11 years ago
- RISC-V RV32IMAFC Core for MCU☆42Feb 1, 2025Updated last year
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆32Nov 6, 2018Updated 7 years ago