avikram2 / RISCVPipelinedProcessorLinks
Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-mapped L1 Data Cache, and a 4-way set-associative L2 Victim Cache with a fully-associative 8-entry Victim Buffer. Also has a tournament branch predictor (global and local predictors) and a set-associative BTB.
☆13Updated 2 years ago
Alternatives and similar repositories for RISCVPipelinedProcessor
Users that are interested in RISCVPipelinedProcessor are comparing it to the libraries listed below
Sorting:
- ☆20Updated 2 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆14Updated 3 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- Design and UVM-TB of RISC -V Microprocessor☆25Updated last year
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆15Updated 5 months ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆24Updated 5 years ago
- YSYX RISC-V Project NJU Study Group☆16Updated 8 months ago
- RTL code of some arbitration algorithm☆14Updated 6 years ago
- ☆10Updated 5 years ago
- UVM Testbench for synchronus fifo☆17Updated 5 years ago
- ☆26Updated 4 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆35Updated 2 years ago
- AXI Interconnect☆52Updated 4 years ago
- ☆35Updated 6 years ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆10Updated 6 years ago
- CORE-V MCU UVM Environment and Test Bench☆24Updated last year
- ☆17Updated 10 years ago
- SoC Based on ARM Cortex-M3☆33Updated 4 months ago
- ☆29Updated 5 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆39Updated 3 years ago
- Maven Silicon Project☆19Updated 6 years ago
- AXI4 with a FIFO integrated with VIP☆21Updated last year
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆25Updated 7 months ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆41Updated 3 years ago
- General Purpose AXI Direct Memory Access☆58Updated last year
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆13Updated 6 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆11Updated last year
- Sample UVM code for axi ram dut☆37Updated 3 years ago