loghall / axi_cache
verification of simple axi-based cache
☆18Updated 5 years ago
Alternatives and similar repositories for axi_cache:
Users that are interested in axi_cache are comparing it to the libraries listed below
- ☆19Updated 2 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆30Updated 2 years ago
- Synchronous FIFO design & verification using systemVerilog Assertions☆15Updated 3 years ago
- ☆17Updated 9 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆11Updated 4 years ago
- CORE-V MCU UVM Environment and Test Bench☆19Updated 7 months ago
- ☆25Updated 3 years ago
- SoC Based on ARM Cortex-M3☆27Updated this week
- ☆12Updated 9 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆48Updated 3 years ago
- The memory model was leveraged from micron.☆22Updated 6 years ago
- ☆14Updated 5 years ago
- Andes Vector Extension support added to riscv-dv☆14Updated 4 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆12Updated 9 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆19Updated 12 years ago
- RTL code of some arbitration algorithm☆13Updated 5 years ago
- AXI Interconnect☆47Updated 3 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆30Updated 6 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆21Updated 6 years ago
- ☆31Updated 5 years ago
- A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…☆14Updated 6 years ago
- Generate UVM testbench framework template files with Python 3☆25Updated 5 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- UVM resource from github, run simulation use YASAsim flow☆27Updated 4 years ago
- AHB-APB UVM Verification Environment☆17Updated 9 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11Updated 3 years ago
- ☆16Updated 5 years ago
- DDR3 function verification environment in UVM☆23Updated 6 years ago
- General Purpose AXI Direct Memory Access☆49Updated 10 months ago
- Implementation of the PCIe physical layer☆33Updated last month