A simple RISC V core for teaching
☆204Dec 30, 2021Updated 4 years ago
Alternatives and similar repositories for riscv-simple-sv
Users that are interested in riscv-simple-sv are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Computer architecture learning environment using FPGAs☆15May 17, 2021Updated 4 years ago
- RISC-V CPU Core (RV32IM)☆1,698Sep 18, 2021Updated 4 years ago
- An Open-Source Design and Verification Environment for RISC-V☆88Apr 21, 2021Updated 4 years ago
- Minimalistic RV32I RISC-V Processor in System Verilog☆26Sep 19, 2023Updated 2 years ago
- Functional verification project for the CORE-V family of RISC-V cores.☆673Updated this week
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆65Jan 13, 2021Updated 5 years ago
- RISC-V microcontroller IP core for embedded, FPGA and ASIC applications☆194Apr 12, 2026Updated last week
- Processing Unit with RISCV-32 / RISCV-64 / RISCV-128☆20Apr 10, 2026Updated last week
- Marginally better than redstone☆104Aug 12, 2020Updated 5 years ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,092Jun 27, 2024Updated last year
- RISC-V Nox core☆72Jul 22, 2025Updated 8 months ago
- SERV - The SErial RISC-V CPU☆1,785Feb 19, 2026Updated 2 months ago
- ☆24Jun 23, 2024Updated last year
- Simple RISC-V 3-stage Pipeline in Chisel☆606Aug 9, 2024Updated last year
- Serverless GPU API endpoints on Runpod - Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆978Nov 15, 2024Updated last year
- RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.☆359Jan 12, 2018Updated 8 years ago
- Quickly update a bitstream with new RAM contents☆16Jun 8, 2021Updated 4 years ago
- RISC-V Assembler☆18Oct 26, 2023Updated 2 years ago
- CORE-V Family of RISC-V Cores☆348Mar 31, 2026Updated 2 weeks ago
- Synthesizable and Parameterized Cache Controller in Verilog☆46Jun 13, 2023Updated 2 years ago
- Synthesize Verilog to Minecraft redstone☆21Nov 9, 2024Updated last year
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆501Apr 9, 2026Updated last week
- Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.☆19Updated this week
- Deploy open-source AI quickly and easily - Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations☆77May 15, 2023Updated 2 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Jan 19, 2021Updated 5 years ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,836Apr 10, 2026Updated last week
- A small, light weight, RISC CPU soft core☆1,536Dec 8, 2025Updated 4 months ago
- 32-bit RISC-V system on chip for iCE40 FPGAs☆314May 25, 2023Updated 2 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Updated this week
- Learning FPGA, yosys, nextpnr, and RISC-V☆3,470Nov 18, 2025Updated 5 months ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆339Dec 11, 2024Updated last year
- Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.☆19Jul 29, 2021Updated 4 years ago
- Serverless GPU API endpoints on Runpod - Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- A MIPS CPU implemented in Verilog☆71Sep 12, 2017Updated 8 years ago
- A simple DDR3 memory controller☆63Jan 9, 2023Updated 3 years ago
- 32 bit RISC-V CPU implementation in Verilog☆34Feb 9, 2022Updated 4 years ago
- 5-stage RISC-V CPU, originally developed for RISCBoy☆37Jul 1, 2023Updated 2 years ago
- A tiny POWER Open ISA soft processor written in Chisel☆114Feb 13, 2023Updated 3 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,213May 26, 2025Updated 10 months ago
- 32-bit Superscalar RISC-V CPU☆1,235Sep 18, 2021Updated 4 years ago