Alternatives and similar repositories for riscv-simple-sv

Users that are interested in riscv-simple-sv are comparing it to the libraries listed below

• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆273Updated last week
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆144Updated 6 years ago
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆415Updated 2 weeks ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆245Updated 10 months ago
• SpinalHDL / NaxRiscv
  ☆297Updated last week
• rafaelcalcada / rvx
  RISC-V microcontroller IP core developed in Verilog
  ☆183Updated 5 months ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆324Updated 9 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆297Updated this week
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆295Updated last year
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆125Updated 6 years ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆387Updated 3 months ago
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆145Updated 5 years ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆211Updated 6 months ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆218Updated 5 years ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆111Updated last year
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆299Updated 7 months ago
• chipsalliance / Cores-VeeR-EH2
  ☆244Updated 2 years ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆532Updated last month
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆311Updated last year
• riscv-ovpsim / imperas-riscv-tests
  ☆189Updated last year
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆187Updated 2 months ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆116Updated this week
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆277Updated 5 years ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆181Updated last week
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆228Updated this week
• subbdue / systemverilog.io
  Code used in
  ☆196Updated 8 years ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆286Updated this week
• lowRISC / style-guides
  lowRISC Style Guides
  ☆457Updated 3 months ago
• chipsalliance / VeeR-ISS
  ☆145Updated last year
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆183Updated 10 months ago