buttercutter / DDR
A simple DDR3 memory controller
☆54Updated 2 years ago
Alternatives and similar repositories for DDR:
Users that are interested in DDR are comparing it to the libraries listed below
- ☆55Updated 4 years ago
- UART -> AXI Bridge☆61Updated 3 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆73Updated 2 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆68Updated 2 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 4 months ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- Repository gathering basic modules for CDC purpose☆53Updated 5 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 4 years ago
- Generic FIFO implementation with optional FWFT☆57Updated 4 years ago
- Xilinx AXI VIP example of use☆38Updated 4 years ago
- Verilog digital signal processing components☆133Updated 2 years ago
- RTL Verilog library for various DSP modules☆86Updated 3 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆102Updated 3 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 4 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆65Updated 7 months ago
- Engineering Program on RTL Design for FPGA Accelerator☆29Updated 4 years ago
- Verilog Content Addressable Memory Module☆104Updated 3 years ago
- ☆25Updated 3 years ago
- General Purpose AXI Direct Memory Access☆49Updated 11 months ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆133Updated last month
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 2 months ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- SDRAM controller with AXI4 interface☆91Updated 5 years ago
- open-source Ethenet media access controller for Ariane on Genesys-2☆18Updated 5 years ago
- UART models for cocotb☆28Updated 2 years ago
- IEEE P1735 decryptor for VHDL☆31Updated 9 years ago
- Extensible FPGA control platform☆59Updated last year
- Platform Level Interrupt Controller☆40Updated 11 months ago
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago