A simple DDR3 memory controller
☆61Jan 9, 2023Updated 3 years ago
Alternatives and similar repositories for DDR
Users that are interested in DDR are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆80Dec 1, 2022Updated 3 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆42Oct 16, 2017Updated 8 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆575Oct 10, 2021Updated 4 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆88Apr 8, 2024Updated last year
- Opensource DDR3 Controller☆423Jan 18, 2026Updated 2 months ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆19Apr 27, 2024Updated last year
- Imaging application using MIPI and DisplayPort to process image☆25Feb 13, 2020Updated 6 years ago
- Quickly update a bitstream with new RAM contents☆16Jun 8, 2021Updated 4 years ago
- Repository containing the DSP gateware cores☆14Mar 9, 2026Updated 2 weeks ago
- verilog core for ws2812 leds☆35Nov 3, 2021Updated 4 years ago
- VHDL package to provide C-like string formatting☆15May 6, 2022Updated 3 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆124Jul 22, 2021Updated 4 years ago
- Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…☆22Feb 4, 2025Updated last year
- ☆19Feb 12, 2026Updated last month
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- This Repo contains SystemC for testBench for AMBA® 3 AHB-Lite Protocol☆13Jul 11, 2018Updated 7 years ago
- A MCU implementation based PODES-M0O☆19Jan 31, 2020Updated 6 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆48May 10, 2024Updated last year
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆12Jul 14, 2024Updated last year
- RTL design for a nasdaq compatible high frequency trading low level. Supports itch on moldudp64.☆81Dec 24, 2023Updated 2 years ago
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆36Dec 24, 2020Updated 5 years ago
- SISO vector decoder for IRA-LDPC codes in VHDL☆12Oct 18, 2022Updated 3 years ago
- To design test bench of the APB protocol☆18Dec 30, 2020Updated 5 years ago
- ☆10Oct 23, 2016Updated 9 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Open source ISS and logic RISC-V 32 bit project☆60Jan 20, 2026Updated 2 months ago
- ☆24Jun 23, 2024Updated last year
- ☆10Jun 9, 2022Updated 3 years ago
- 12 bit SAR ADC for TinyTapeout 7☆15May 30, 2024Updated last year
- Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.☆39Jan 19, 2026Updated 2 months ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆23Jul 6, 2018Updated 7 years ago
- A Visual RISC-V Simulator☆16Nov 7, 2023Updated 2 years ago
- Matrix Multiplication in Hardware☆16Jun 3, 2020Updated 5 years ago
- A tiny 3-stage RISC-V core written in Chisel.☆16Apr 14, 2023Updated 2 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Small footprint and configurable DRAM core☆480Mar 13, 2026Updated last week
- Miscellaneous prototype hardware that wasn't major enough to warrant a dedicated repo☆17Aug 1, 2025Updated 7 months ago
- VHDL sources for a BT.656 to axi4-stream converter☆12Mar 20, 2023Updated 3 years ago
- ☆13Jul 28, 2022Updated 3 years ago
- This project contains Verilog designs and a PCB for the implementation of CSI-2 camera interface to HDMI bridge on a Gatemate FPGA from C…☆19Jul 28, 2025Updated 7 months ago
- General Purpose AXI Direct Memory Access☆64May 12, 2024Updated last year
- An Open Source Link Protocol and Controller☆28Aug 1, 2021Updated 4 years ago