Alternatives and similar repositories for DDR

Users that are interested in DDR are comparing it to the libraries listed below

• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆79Updated 3 years ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆58Updated 6 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆53Updated 2 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆81Updated last month
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆70Updated 4 years ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆122Updated 4 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆82Updated 3 years ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆55Updated last year
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆62Updated last year
• wyvernSemi / pcievhost
  PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities
  ☆132Updated last week
• shuckc / verilog-utils
  native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches
  ☆46Updated 11 years ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆60Updated 3 weeks ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆48Updated 4 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆44Updated last year
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆43Updated 4 years ago
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆97Updated 4 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆148Updated last week
• vsdip / vsdsram_sky130
  ☆41Updated 3 years ago
• tomverbeure / math
  SpinalHDL Hardware Math Library
  ☆96Updated last year
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆19Updated last year
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆77Updated 6 months ago
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆82Updated 4 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆34Updated last year
• aignacio / nox
  RISC-V Nox core
  ☆71Updated 6 months ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆53Updated 6 years ago
• antmicro / cocotb-verilator-build
  ☆26Updated 2 years ago
• zebmehring / Processor-Cache
  A Verilog implementation of a processor cache.
  ☆36Updated 8 years ago
• alexforencich / cocotbext-eth
  Ethernet interface modules for Cocotb
  ☆75Updated 5 months ago
• yigitbektasgursoy / SDRAM_Verilog
  Verilog HDL implementation of SDRAM controller and SDRAM model
  ☆40Updated last year
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆61Updated 5 years ago