Minimalistic RV32I RISC-V Processor in System Verilog
☆37Sep 6, 2026Updated last month
Alternatives and similar repositories for RV32I
Users that are interested in RV32I are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RV64IMAC modelling using System Verilog HDL☆28Aug 15, 2026Updated last month
- 32-bit 5-stage pipelined RISC-V processor in SystemVerilog☆45Oct 29, 2023Updated 2 years ago
- North Carolina State University: ECE 745 : Project: LC3 Microcontroller Functional Verification using SystemVerilog☆11Jun 5, 2017Updated 9 years ago
- Used for hardware trojan detection（Based on Trust_Hub）☆10Jul 30, 2019Updated 7 years ago
- Matrak Verilog ile yazılmış bir RISC-V işlemcidir.☆11May 8, 2024Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆17Jun 24, 2020Updated 6 years ago
- A Verilog RTL model of a simple 8-bit RISC processor☆21Jan 15, 2019Updated 7 years ago
- APB verification using UVM☆15Sep 7, 2026Updated last month
- ☆11Nov 30, 2022Updated 3 years ago
- pcie datalink layer implementation in verilog/systemverilog☆18Sep 10, 2026Updated last month
- A Verilog based 5-stage fully functional pipelined RISC-V Processor code.☆77May 8, 2021Updated 5 years ago
- risc-v-myth-workshop-august-Redbeard358 created by GitHub Classroom☆19Sep 15, 2020Updated 6 years ago
- A chess implementation in C++ with many player AIs, including a neural-network-powered AI not unlike Deepmind's AlphaZero chess engine...…☆23Dec 28, 2020Updated 5 years ago
- Открытое RISC-V процессорное ядро MIRISCV для образовательных целей☆32Dec 5, 2024Updated last year
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- FPGA raycaster engine written in verilog☆16Apr 19, 2019Updated 7 years ago
- Simple key value pairs store only integer and string types.☆12Nov 5, 2018Updated 7 years ago
- Vietnamese ID information detection☆19Jun 24, 2022Updated 4 years ago
- ARMv7 Single-Cycle processor implementation in Logisim☆13Sep 20, 2022Updated 4 years ago
- Machine Learning Techniques for Hardware Trojan Detection☆28Sep 24, 2020Updated 6 years ago
- A Python based 8085 assembler.☆13Feb 18, 2025Updated last year
- ☆35Nov 4, 2024Updated last year
- "Structured programming" macros for Gnu Assembler (gas)☆17Feb 23, 2026Updated 7 months ago
- Another tiny RISC-V implementation☆68Jul 19, 2021Updated 5 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…☆76Aug 10, 2024Updated 2 years ago
- A SoC for DOOM☆20Apr 11, 2021Updated 5 years ago
- A Single Cycle Risc-V 32 bit CPU☆78Jan 14, 2026Updated 8 months ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆31Jun 22, 2024Updated 2 years ago
- ☆45Jul 20, 2023Updated 3 years ago
- A Daemon for Real-Time Detection of Cache Side-Channel Attacks☆19Jun 21, 2026Updated 3 months ago
- A mixed-signal system on chip for nanopore-based DNA sequencing☆35Nov 30, 2022Updated 3 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆40Nov 6, 2022Updated 3 years ago
- Hardware Agent☆36Updated this week
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- SystemVerilog UVM testbench example☆38May 8, 2024Updated 2 years ago
- A simple RISC V core for teaching☆216Jun 2, 2026Updated 4 months ago
- Final Project for Digital Systems Design Course, Fall 2020☆17Jul 20, 2022Updated 4 years ago
- Microarchitectural control flow integrity (𝜇CFI) verification checks whether there exists a control or data flow from instruction's ope…☆16Jul 2, 2026Updated 3 months ago
- The purpose of the repo is to support CORE-V Wally architectural verification☆20Nov 11, 2025Updated 11 months ago
- "Designing Video Game Hardware in Verilog" in iCE40HX8K Breakout Board.☆18Dec 31, 2019Updated 6 years ago
- Design and verify the AMBA AXI protocol with single master-slave from scratch in System Verilog. Debugging the design using both a System…☆13Oct 8, 2017Updated 9 years ago