antonblanchard / chiselwattLinks
A tiny POWER Open ISA soft processor written in Chisel
☆111Updated 2 years ago
Alternatives and similar repositories for chiselwatt
Users that are interested in chiselwatt are comparing it to the libraries listed below
Sorting:
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆80Updated 3 years ago
- Project X-Ray Database: XC7 Series☆73Updated 3 years ago
- SoftCPU/SoC engine-V☆55Updated 7 months ago
- ☆63Updated 6 years ago
- Experiments with fixed function renderers and Chisel HDL☆59Updated 6 years ago
- SoC based on VexRiscv and ICE40 UP5K☆158Updated 7 months ago
- PicoRV☆43Updated 5 years ago
- CoreScore☆167Updated 3 weeks ago
- MR1 formally verified RISC-V CPU☆53Updated 6 years ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆75Updated 6 years ago
- The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …☆50Updated 5 months ago
- Naive Educational RISC V processor☆91Updated last month
- Demo SoC for SiliconCompiler.☆62Updated 2 weeks ago
- FPGA reference design for the the Swerv EH1 Core☆72Updated 5 years ago
- FPGA Assembly (FASM) Parser and Generator☆97Updated 3 years ago
- OmniXtend cache coherence protocol☆82Updated 5 months ago
- Featherweight RISC-V implementation☆53Updated 3 years ago
- FuseSoC standard core library☆148Updated 5 months ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 6 months ago
- Yet Another RISC-V Implementation☆98Updated last year
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆44Updated 3 years ago
- 😎 A curated list of awesome RISC-V implementations☆138Updated 2 years ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆102Updated 4 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- A utility for Composing FPGA designs from Peripherals☆185Updated 10 months ago
- A Verilog Synthesis Regression Test☆37Updated last year
- A single-wire bi-directional chip-to-chip interface for FPGAs☆123Updated 9 years ago
- Bitstream relocation and manipulation tool.☆48Updated 2 years ago