antonblanchard / chiselwattLinks
A tiny POWER Open ISA soft processor written in Chisel
☆110Updated 2 years ago
Alternatives and similar repositories for chiselwatt
Users that are interested in chiselwatt are comparing it to the libraries listed below
Sorting:
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆80Updated 3 years ago
- Project X-Ray Database: XC7 Series☆70Updated 3 years ago
- SoftCPU/SoC engine-V☆54Updated 4 months ago
- The specification for the FIRRTL language☆59Updated last week
- FPGA Assembly (FASM) Parser and Generator☆94Updated 3 years ago
- A utility for Composing FPGA designs from Peripherals☆182Updated 7 months ago
- ☆64Updated 6 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆88Updated 6 years ago
- Naive Educational RISC V processor☆85Updated 2 weeks ago
- PicoRV☆44Updated 5 years ago
- Bitstream relocation and manipulation tool.☆47Updated 2 years ago
- Experiments with fixed function renderers and Chisel HDL☆59Updated 6 years ago
- CoreScore☆159Updated 6 months ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆75Updated 6 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- A single-wire bi-directional chip-to-chip interface for FPGAs☆124Updated 9 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago
- 😎 A curated list of awesome RISC-V implementations☆137Updated 2 years ago
- Yet Another RISC-V Implementation☆96Updated 10 months ago
- MR1 formally verified RISC-V CPU☆53Updated 6 years ago
- Demo SoC for SiliconCompiler.☆60Updated 2 months ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆90Updated 6 years ago
- Lipsi: Probably the Smallest Processor in the World☆86Updated last year
- A reimplementation of a tiny stack CPU☆85Updated last year
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆178Updated 2 months ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- OmniXtend cache coherence protocol☆82Updated last month
- Featherweight RISC-V implementation☆52Updated 3 years ago
- SoC based on VexRiscv and ICE40 UP5K☆159Updated 4 months ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆66Updated this week