antonblanchard / chiselwattLinks
A tiny POWER Open ISA soft processor written in Chisel
☆108Updated 2 years ago
Alternatives and similar repositories for chiselwatt
Users that are interested in chiselwatt are comparing it to the libraries listed below
Sorting:
- Project X-Ray Database: XC7 Series☆69Updated 3 years ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆78Updated 3 years ago
- SoftCPU/SoC engine-V☆54Updated 3 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆114Updated last year
- ☆63Updated 6 years ago
- SoC based on VexRiscv and ICE40 UP5K☆158Updated 3 months ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆89Updated 5 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆175Updated last month
- Naive Educational RISC V processor☆84Updated 2 weeks ago
- OmniXtend cache coherence protocol☆82Updated 2 weeks ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago
- MR1 formally verified RISC-V CPU☆53Updated 6 years ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆123Updated 8 years ago
- System on Chip toolkit for Amaranth HDL☆91Updated 8 months ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- A utility for Composing FPGA designs from Peripherals☆179Updated 6 months ago
- Demo SoC for SiliconCompiler.☆59Updated 3 weeks ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- PicoRV☆44Updated 5 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆64Updated 3 weeks ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆136Updated 3 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆105Updated last month
- ☆79Updated last year
- Yet Another RISC-V Implementation☆93Updated 9 months ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆87Updated 5 years ago
- FuseSoC standard core library☆143Updated 3 weeks ago
- Mutation Cover with Yosys (MCY)☆84Updated 2 weeks ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago