Alternatives and similar repositories for chiselwatt:

Users that are interested in chiselwatt are comparing it to the libraries listed below

• f4pga / prjuray
  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
  ☆75Updated 3 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆129Updated 2 months ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆66Updated 3 years ago
• chipsalliance / omnixtend
  OmniXtend cache coherence protocol
  ☆79Updated 4 years ago
• cliffordwolf / PonyLink
  A single-wire bi-directional chip-to-chip interface for FPGAs
  ☆117Updated 8 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last week
• cornell-brg / lizard
  Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL
  ☆87Updated 5 years ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆59Updated 3 weeks ago
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 6 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 5 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆68Updated 2 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆83Updated last week
• ucb-bar / zscale
  Z-scale Microarchitectural Implementation of RV32 ISA
  ☆55Updated 7 years ago
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆134Updated 3 years ago
• pieter3d / simview
  ☆77Updated last year
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆114Updated 4 months ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆101Updated 3 years ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆154Updated last week
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆172Updated 8 months ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆71Updated 5 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆62Updated 2 weeks ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆60Updated 10 months ago
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆87Updated 5 years ago
• olofk / corescore
  CoreScore
  ☆144Updated 2 months ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆79Updated 5 months ago
• IBM / hdl-tools
  Facilitates building open source tools for working with hardware description languages (HDLs)
  ☆63Updated 5 years ago
• PrincetonUniversity / prga
  Open-source FPGA research and prototyping framework.
  ☆203Updated 7 months ago
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆175Updated 3 months ago