antonblanchard / chiselwattLinks
A tiny POWER Open ISA soft processor written in Chisel
☆109Updated 2 years ago
Alternatives and similar repositories for chiselwatt
Users that are interested in chiselwatt are comparing it to the libraries listed below
Sorting:
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆79Updated 3 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- Project X-Ray Database: XC7 Series☆70Updated 3 years ago
- SoftCPU/SoC engine-V☆54Updated 3 months ago
- ☆63Updated 6 years ago
- OmniXtend cache coherence protocol☆82Updated last month
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆88Updated 5 years ago
- Demo SoC for SiliconCompiler.☆59Updated last month
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- Mutation Cover with Yosys (MCY)☆85Updated this week
- MR1 formally verified RISC-V CPU☆53Updated 6 years ago
- Bitstream relocation and manipulation tool.☆47Updated 2 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆115Updated last year
- Experiments with fixed function renderers and Chisel HDL☆59Updated 6 years ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆124Updated 9 years ago
- Yet Another RISC-V Implementation☆94Updated 9 months ago
- Xilinx Unisim Library in Verilog☆78Updated 4 years ago
- The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …☆48Updated last month
- A utility for Composing FPGA designs from Peripherals☆181Updated 6 months ago
- SoC based on VexRiscv and ICE40 UP5K☆158Updated 3 months ago
- The specification for the FIRRTL language☆58Updated last week
- PicoRV☆44Updated 5 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆89Updated 6 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆65Updated last week
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- Lipsi: Probably the Smallest Processor in the World☆86Updated last year
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆74Updated 6 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 2 months ago