Alternatives and similar repositories for chiselwatt:

Users that are interested in chiselwatt are comparing it to the libraries listed below

• f4pga / prjuray
  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
  ☆76Updated 3 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated 3 weeks ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆173Updated 8 months ago
• tomverbeure / mr1
  MR1 formally verified RISC-V CPU
  ☆54Updated 6 years ago
• cornell-brg / lizard
  Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL
  ☆88Updated 5 years ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆156Updated last month
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 6 years ago
• chipsalliance / omnixtend
  OmniXtend cache coherence protocol
  ☆80Updated 4 years ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆141Updated last month
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆73Updated 6 years ago
• cliffordwolf / PonyLink
  A single-wire bi-directional chip-to-chip interface for FPGAs
  ☆119Updated 8 years ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆155Updated 4 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆92Updated last month
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆52Updated 3 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 5 years ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆80Updated last week
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆133Updated 2 weeks ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆83Updated 4 years ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆80Updated 6 months ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆69Updated 2 years ago
• pieter3d / simview
  ☆77Updated last year
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆87Updated 5 years ago
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆134Updated 3 years ago
• laforest / Octavo
  Verilog FPGA Parts Library. Old Octavo soft-CPU project.
  ☆74Updated 6 years ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆113Updated last year
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆91Updated 6 months ago
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆66Updated 3 years ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆75Updated 4 years ago
• jbush001 / ChiselGPU
  Experiments with fixed function renderers and Chisel HDL
  ☆59Updated 6 years ago