A tiny POWER Open ISA soft processor written in Chisel
☆117Feb 13, 2023Updated 3 years ago
Alternatives and similar repositories for chiselwatt
Users that are interested in chiselwatt are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A tiny Open POWER ISA softcore written in VHDL 2008☆729Aug 12, 2026Updated 2 months ago
- A RISC-V assembler library for Scala/Chisel HDL projects☆16Aug 27, 2026Updated 2 months ago
- ☆147Apr 5, 2022Updated 4 years ago
- PLEASE MOVE TO PAWSv2☆16Feb 2, 2022Updated 4 years ago
- Provides dot visualizations of chisel/firrtl circuites☆13Mar 12, 2019Updated 7 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆247Aug 12, 2022Updated 4 years ago
- A 32-bit RISC-V soft processor☆329Jan 26, 2026Updated 9 months ago
- BFM Tester for Chisel HDL☆14Nov 27, 2021Updated 4 years ago
- Standard HyperRAM core for ECP5 written in Litex/Migen☆14Dec 6, 2019Updated 6 years ago
- ☆20Feb 9, 2020Updated 6 years ago
- ☆12Dec 22, 2020Updated 5 years ago
- ☆21Mar 3, 2026Updated 7 months ago
- Common RTL blocks used in SiFive's projects☆194May 13, 2022Updated 4 years ago
- Lipsi: Probably the Smallest Processor in the World☆90Apr 15, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Chisel/Firrtl execution engine☆157Aug 21, 2024Updated 2 years ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆225Jan 23, 2020Updated 6 years ago
- An example OMI Device FPGA with 2 DDR4 memory ports☆20Jan 5, 2023Updated 3 years ago
- User-friendly explanation of Yosys options☆114Sep 25, 2021Updated 5 years ago
- Programmable multichannel ADPCM decoder for FPGA☆26Dec 28, 2020Updated 5 years ago
- A soft multimedia/graphics processor prototype in Chisel 3☆11May 3, 2023Updated 3 years ago
- A RISC-V Core (RV32I) written in Chisel HDL☆110Oct 19, 2026Updated 2 weeks ago
- Cross compile FPGA tools☆21Jan 4, 2021Updated 5 years ago
- uIP 0.9 PicoSoC/PicoRV32 port☆11Apr 7, 2018Updated 8 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- A configurable SRAM generator☆72Oct 20, 2026Updated last week
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- Chisel Things for OFDM☆33Jul 1, 2020Updated 6 years ago
- OmniXtend cache coherence protocol☆85Jun 10, 2025Updated last year
- Wishbone plumbing written in Chisel3☆10Dec 19, 2024Updated last year
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆132Mar 6, 2026Updated 7 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆123Sep 20, 2023Updated 3 years ago
- For contributions of Chisel IP to the chisel community.☆73Sep 17, 2026Updated last month
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe☆103May 16, 2023Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- basic example of litex on colorLight 5A-75B based on fpga_101/lab004☆39Jan 11, 2023Updated 3 years ago
- Library to compile Chisel circuits using LLVM/MLIR (CIRCT)☆70Mar 2, 2023Updated 3 years ago
- A Library of Chisel3 Tools for Digital Signal Processing☆251Apr 29, 2024Updated 2 years ago
- A dynamic verification library for Chisel.☆163Nov 9, 2024Updated last year
- RISC-V GPGPU☆40Mar 6, 2020Updated 6 years ago
- Chisel components for FPGA projects☆129Sep 19, 2023Updated 3 years ago
- (System)Verilog to Chisel translator☆125May 20, 2022Updated 4 years ago