antonblanchard / chiselwattLinks
A tiny POWER Open ISA soft processor written in Chisel
☆114Updated 2 years ago
Alternatives and similar repositories for chiselwatt
Users that are interested in chiselwatt are comparing it to the libraries listed below
Sorting:
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆82Updated 4 years ago
- Project X-Ray Database: XC7 Series☆74Updated 4 years ago
- SoftCPU/SoC engine-V☆55Updated 10 months ago
- ☆63Updated 7 years ago
- Mutation Cover with Yosys (MCY)☆91Updated this week
- FPGA Assembly (FASM) Parser and Generator☆99Updated 3 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆92Updated 6 years ago
- PicoRV☆43Updated 5 years ago
- CoreScore☆172Updated 2 months ago
- Bitstream relocation and manipulation tool.☆51Updated 3 years ago
- Naive Educational RISC V processor☆94Updated 3 months ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆125Updated 9 years ago
- Experiments with fixed function renderers and Chisel HDL☆60Updated 6 years ago
- User-friendly explanation of Yosys options☆113Updated 4 years ago
- The specification for the FIRRTL language☆62Updated last week
- A utility for Composing FPGA designs from Peripherals☆186Updated last year
- 😎 A curated list of awesome RISC-V implementations☆142Updated 2 years ago
- Lipsi: Probably the Smallest Processor in the World☆89Updated last year
- A Verilog Synthesis Regression Test☆37Updated 3 weeks ago
- Demo SoC for SiliconCompiler.☆62Updated last week
- FPGA reference design for the the Swerv EH1 Core☆72Updated 6 years ago
- OmniXtend cache coherence protocol☆82Updated 8 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆70Updated last month
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆76Updated 6 years ago
- Featherweight RISC-V implementation☆53Updated 4 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 6 years ago
- SoC based on VexRiscv and ICE40 UP5K☆161Updated 10 months ago
- Using VexRiscv without installing Scala☆39Updated 4 years ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆109Updated 4 years ago