Alternatives and similar repositories for fpga_quick_ram_update

Users that are interested in fpga_quick_ram_update are comparing it to the libraries listed below

• lawrie / tiny_ram_soc
  Picorv32 SoC that uses only BRAM, not flash memory
  ☆13Updated 7 years ago
• VHDPlus / VHDPlus_Libraries_and_Examples
  This is a collection of the built in libraries of the VHDPlus IDE toghether with examples. Commits will be featured in the IDE with futur…
  ☆20Updated last year
• tmeissner / gatemate_experiments
  Experiments with Cologne Chip's GateMate FPGA architecture
  ☆17Updated 2 years ago
• tomverbeure / jtag_uart_example
  Mini CPU design with JTAG UART support
  ☆21Updated 4 years ago
• GMM-7550 / gmm7550-hardware
  CologneChip GateMate FPGA Module: GMM-7550
  ☆28Updated 2 weeks ago
• hdl-util / i2c
  Fully featured implementation of Inter-IC (I2C) bus master for FPGAs
  ☆32Updated 5 years ago
• dan-rodrigues / mobile-fpga-bluetooth-demo
  Simple BLE demo using an iOS app (SwiftUI), an ESP32 (Python) and an FPGA (Verilog)
  ☆15Updated 5 years ago
• lawrie / ulx3s_bit_streams
  Bit streams forthe Ulx3s ECP5 device
  ☆18Updated 2 years ago
• hansfbaier / colorlight-qmtech-adapter
  Adapter to use Colorlight i5/i9 FPGA boards in a QMTech board form factor
  ☆20Updated 3 years ago
• tomverbeure / ecp5_jtag
  Use ECP5 JTAG port to interact with user design
  ☆33Updated 4 years ago
• tomverbeure / intel_jtag_primitive_blog
  How to use the Intel JTAG primitive without using virtual JTAG
  ☆17Updated 4 years ago
• jevinskie / General-Slow-DDR3-Interface
  A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.
  ☆11Updated 3 years ago
• lawrie / ulx3s_examples
  Example Verilog code for Ulx3s
  ☆41Updated 3 years ago
• hdl-util / vga-text-mode
  VGA-compatible text mode functionality
  ☆17Updated 5 years ago
• lawrie / ulx3s_retro
  Retro computing on the Ulx3s ECP5 FPGA board
  ☆25Updated 3 years ago
• mattvenn / logLUTs
  Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.
  ☆22Updated 2 years ago
• juliancoy / openStreamHDL
  VHDL Code for infrastructural blocks (designed for FPGA)
  ☆15Updated 3 years ago
• defparam / PCI2Nano-RTL
  An open source FPGA PCI core & 8250-Compatible PCI UART core
  ☆46Updated 5 years ago
• rob-ng15 / PAWS
  PLEASE MOVE TO PAWSv2
  ☆16Updated 4 years ago
• kazkojima / lunauac2-pdm
  A LiteX module implementing a USB UAC2 module with simple PDM in/out
  ☆16Updated 3 years ago
• nockieboy / gpu
  Collaborative project to create an advanced GPU, with additional features to flesh-out the peripherals for a home-made, DIY computer.
  ☆18Updated 2 years ago
• gtjennings1 / HyperBUS
  A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs
  ☆63Updated 7 years ago
• xobs / lxbuildenv
  Simplified environment for litex
  ☆14Updated 5 years ago
• tomverbeure / usb_system
  SpinalHDL USB system for the ULPI based Arrow DECA board
  ☆20Updated 4 years ago
• ironsteel / nes_ecp5
  NES FPGA implementation synthesized for the ulx3s ecp5 based fpga board
  ☆38Updated 3 weeks ago
• dan-rodrigues / ics-adpcm
  Programmable multichannel ADPCM decoder for FPGA
  ☆25Updated 5 years ago
• OLIMEX / GateMateA1-EVB
  Development board for GateMateA1 CCGM1A1 FPGA from Cologne Chip with PS2 VGA 64Mbit RAM RP2040
  ☆36Updated last month
• lawrie / blackicemxbook
  ☆27Updated 6 years ago
• no2fpga / no2muacm
  Drop In USB CDC ACM core for iCE40 FPGA
  ☆34Updated 4 years ago
• abnoname / iceZ0mb1e
  FPGA 8-Bit TV80 SoC for Lattice iCE40 with complete open-source toolchain flow using yosys and SDCC
  ☆58Updated 3 years ago