Computer architecture learning environment using FPGAs
☆15May 17, 2021Updated 5 years ago
Alternatives and similar repositories for riscv-simple
Users that are interested in riscv-simple are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A simple RISC V core for teaching☆216Jun 2, 2026Updated 5 months ago
- 32-bit soft RISCV processor for FPGA applications☆20Nov 25, 2023Updated 2 years ago
- FIR,FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- List all available information about all SYCL devices and platforms☆15Sep 14, 2020Updated 6 years ago
- RiscV cpu on FPGA☆13Apr 23, 2022Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- This is a Verilog controller for SSD1306 0.96'' OLED display.☆12Aug 4, 2023Updated 3 years ago
- Simple library for decoding RISC-V instructions☆23Jun 21, 2026Updated 4 months ago
- this repository contains all the ip projects presented in the HLS/RISC-V/Computer Architecture book written by Goossens and published by …☆30Sep 5, 2025Updated last year
- A very simple VGA controller written in verilog☆25Jun 1, 2012Updated 14 years ago
- An FPGA-based RISC-V CPU☆16Dec 7, 2021Updated 4 years ago
- A Goldschmidt integer divider written in verilog. Similar to Newton-Raphson but the divison step can be pipelined.☆16Apr 25, 2024Updated 2 years ago
- Pipelined RISC-V RV32I Core in Verilog☆43Apr 9, 2023Updated 3 years ago
- ☆14Dec 9, 2025Updated 10 months ago
- Processing Unit with RISCV-32 / RISCV-64 / RISCV-128☆20Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- CORDIC VLSI-IP for deep learning activation functions☆15Jul 13, 2019Updated 7 years ago
- Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.☆20Jul 29, 2021Updated 5 years ago
- A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL☆99Dec 5, 2019Updated 6 years ago
- Modified version of PULP Ara to support Vector Cryptography (Zvk) Instructions☆17Jan 21, 2026Updated 9 months ago
- PDM bitstream FIR filter☆10Feb 16, 2017Updated 9 years ago
- Verilog VPI VGA Simulator using SDL☆11Feb 9, 2015Updated 11 years ago
- This is a SystemVerilog HDL implementation of Karatsuba multiplier.☆11Jul 8, 2020Updated 6 years ago
- Realtime audio DSP on the ZyBo☆10Jan 25, 2016Updated 10 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆85Jul 18, 2026Updated 3 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Adding UVM support to Icarus Verilog (and Verilator in near future) by taking a step-by-step, bottom-up approach.☆23Dec 27, 2022Updated 3 years ago
- Digital circuit simulator, written by Jeffery P. Hansen☆11Aug 29, 2019Updated 7 years ago
- This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.☆18Mar 17, 2023Updated 3 years ago
- An indoor positioning system relying on time difference of arrival measurements of ultrasonic pings from fixed transmitters.☆12May 15, 2015Updated 11 years ago
- RISC-V Rocket on the Digilent Zybo Board☆21Aug 6, 2014Updated 12 years ago
- ☆13Jun 9, 2022Updated 4 years ago
- RISC-V instruction set extensions for SM4 block cipher☆22Mar 6, 2020Updated 6 years ago
- APB Timer Unit☆14Oct 30, 2025Updated last year
- Wallace and Dadda tree multiplier generator in vhdl and verilog☆14Mar 14, 2026Updated 7 months ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- APB4 Multiplexor☆15May 10, 2024Updated 2 years ago
- Python module/package to read, handle and operate on HDF5 files generated by Multi Channel Systems MCS GmbH software☆12May 19, 2022Updated 4 years ago
- A port from Arjo's uSpeech library (originally intended for Arduino)☆14Jan 6, 2016Updated 10 years ago
- Edge Impulse firmware for Nordic Thingy91☆13Updated this week
- Simulator that maintains coherent caches for 4, 8 and 16 core CMP. Implementation of MSI, MESI, MOSI, MOESI and MOESIF protocols for a b…☆11Jan 6, 2015Updated 11 years ago
- ☆17Aug 25, 2026Updated 2 months ago
- An introduction to singularity☆13Dec 3, 2024Updated last year