sxtyzhangzk / mips-cpu
A MIPS CPU implemented in Verilog
☆66Updated 7 years ago
Alternatives and similar repositories for mips-cpu:
Users that are interested in mips-cpu are comparing it to the libraries listed below
- RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.☆252Updated 7 years ago
- A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL☆78Updated 5 years ago
- Various caches written in Verilog-HDL☆115Updated 9 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆205Updated 4 years ago
- A classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cach…☆75Updated 3 months ago
- a training-target implementation of rv32im, designed to be simple and easy to understand☆56Updated 3 years ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆123Updated 5 years ago
- ☆63Updated 2 years ago
- An out-of-order execution algorithm for pipeline CPU, implemented by verilog☆39Updated 6 years ago
- Pipelined RISC-V CPU☆23Updated 3 years ago
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆181Updated 2 weeks ago
- Naïve MIPS32 SoC implementation☆113Updated 4 years ago
- ☆31Updated last year
- A softcore microprocessor of MIPS32 architecture.☆39Updated 7 months ago
- Wrapper for Rocket-Chip on FPGAs☆129Updated 2 years ago
- Asymmetric dual issue in-order microprocessor.☆34Updated 5 years ago
- Comment on the rocket-chip source code☆171Updated 6 years ago
- Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder☆106Updated 12 years ago
- Verilog Configurable Cache☆170Updated 2 months ago
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆46Updated last year
- Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy☆40Updated 8 years ago
- Simple RISC-V 3-stage Pipeline in Chisel☆559Updated 6 months ago
- chipyard in mill :P☆77Updated last year
- ☆79Updated last week
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- Instruction Set Generator initially contributed by Futurewei☆272Updated last year
- Modern co-simulation framework for RISC-V CPUs☆133Updated this week
- Vector processor for RISC-V vector ISA☆113Updated 4 years ago
- Basic floating-point components for RISC-V processors☆64Updated 5 years ago
- RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.☆336Updated 7 years ago