sxtyzhangzk / mips-cpuLinks
A MIPS CPU implemented in Verilog
☆70Updated 8 years ago
Alternatives and similar repositories for mips-cpu
Users that are interested in mips-cpu are comparing it to the libraries listed below
Sorting:
- RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.☆309Updated 7 years ago
- A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL☆93Updated 5 years ago
- Various caches written in Verilog-HDL☆126Updated 10 years ago
- An out-of-order execution algorithm for pipeline CPU, implemented by verilog☆42Updated 7 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆217Updated 5 years ago
- Comment on the rocket-chip source code☆179Updated 6 years ago
- Wrapper for Rocket-Chip on FPGAs☆137Updated 3 years ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- ☆30Updated 7 months ago
- A classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cach…☆75Updated 11 months ago
- Lipsi: Probably the Smallest Processor in the World☆87Updated last year
- Chisel examples and code snippets☆259Updated 3 years ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆57Updated 2 years ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- a training-target implementation of rv32im, designed to be simple and easy to understand☆61Updated 3 years ago
- Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …☆140Updated 3 years ago
- Chisel Learning Journey☆110Updated 2 years ago
- Labs to learn SpinalHDL☆149Updated last year
- IEEE 754 floating point unit in Verilog☆145Updated 9 years ago
- A Tiny Processor Core☆112Updated 3 months ago
- RISC-V Torture Test☆200Updated last year
- An open source CPU design and verification platform for academia☆111Updated last month
- Verilog Configurable Cache☆184Updated 10 months ago
- 通过issue和README来记录日常学习研究笔记 关注 机器学习系统,深度学习, LLVM,性能剖视, Linux操作系统内核 话题 关注 C/C++. JAVA. Python. Golang. Chisel. 编程语言话题 ( Writing Blogs using …☆77Updated 5 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆163Updated 5 years ago
- Vector processor for RISC-V vector ISA☆128Updated 4 years ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆232Updated 10 months ago
- ☆190Updated last year
- A small SoC with a pipeline 32-bit RISC-V CPU.☆65Updated 3 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 5 months ago