sxtyzhangzk / mips-cpuLinks
A MIPS CPU implemented in Verilog
☆68Updated 7 years ago
Alternatives and similar repositories for mips-cpu
Users that are interested in mips-cpu are comparing it to the libraries listed below
Sorting:
- RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.☆290Updated 7 years ago
- A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL☆83Updated 5 years ago
- An out-of-order execution algorithm for pipeline CPU, implemented by verilog☆40Updated 7 years ago
- Various caches written in Verilog-HDL☆124Updated 10 years ago
- A classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cach…☆74Updated 7 months ago
- a training-target implementation of rv32im, designed to be simple and easy to understand☆60Updated 3 years ago
- ☆34Updated 5 years ago
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆48Updated last year
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆130Updated 5 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆214Updated 4 years ago
- ☆64Updated 2 years ago
- ☆31Updated 3 months ago
- Naïve MIPS32 SoC implementation☆115Updated 5 years ago
- Pipelined RISC-V CPU☆23Updated 4 years ago
- Comment on the rocket-chip source code☆179Updated 6 years ago
- Asymmetric dual issue in-order microprocessor.☆34Updated 5 years ago
- ☆68Updated 4 months ago
- A softcore microprocessor of MIPS32 architecture.☆40Updated 11 months ago
- Wrapper for Rocket-Chip on FPGAs☆134Updated 2 years ago
- ☆72Updated 2 months ago
- A small SoC with a pipeline 32-bit RISC-V CPU.☆65Updated 3 years ago
- Open source high performance IEEE-754 floating unit☆75Updated last year
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆203Updated 2 weeks ago
- Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC(精简指令集)CPU(中央处理器)简单结构和Verilog实现。☆146Updated 6 years ago
- chipyard in mill :P☆78Updated last year
- A simple RISC-V CPU written in Verilog.☆64Updated 10 months ago
- An open source CPU design and verification platform for academia☆103Updated 4 years ago
- MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support☆106Updated 6 years ago
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- 通过issue和README来记录日常学习研究笔记 关注 机器学习系统,深度学习, LLVM,性能剖视, Linux操作系统内核 话题 关注 C/C++. JAVA. Python. Golang. Chisel. 编程语言话题 ( Writing Blogs using …☆77Updated 5 years ago