aziesemer / astranLinks
ASTRAN - Automatic Synthesis of Transistor Networks
☆62Updated 3 years ago
Alternatives and similar repositories for astran
Users that are interested in astran are comparing it to the libraries listed below
Sorting:
- IDEA project source files☆107Updated 8 months ago
- Qrouter detail router for digital ASIC designs☆57Updated 3 months ago
- ☆55Updated last year
- AMC: Asynchronous Memory Compiler☆49Updated 5 years ago
- BAG framework☆41Updated 11 months ago
- ☆113Updated 4 years ago
- Netgen complete LVS tool for comparing SPICE or verilog netlists☆120Updated 2 months ago
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- EDA physical synthesis optimization kit☆59Updated last year
- ☆25Updated 2 years ago
- Global Router Built for ICCAD Contest 2019☆31Updated 5 years ago
- Intel's Analog Detailed Router☆39Updated 6 years ago
- DATC Robust Design Flow.☆37Updated 5 years ago
- An automatic clock gating utility☆50Updated 3 months ago
- UCSD Detailed Router☆89Updated 4 years ago
- Tools for working with circuits as graphs in python☆121Updated last year
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆56Updated 4 years ago
- This is the repository of IPs of the group in USC who is developing Analog Mixed-signal Parameter Search Engine (AMPSE). You can download…☆25Updated 2 years ago
- RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA☆90Updated 5 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits☆62Updated last year
- Material for OpenROAD Tutorial at DAC 2020☆47Updated 2 years ago
- Open Source Detailed Placement engine☆38Updated 5 years ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆27Updated 4 years ago
- Open-source repository for a standard-cell library characterizer using complete open-source tools☆35Updated this week
- Open source process design kit for 28nm open process☆59Updated last year
- BAG2 workspace for fake PDK (cds_ff_mpt)☆58Updated 5 years ago
- ☆76Updated this week
- VLSI EDA Global Router☆73Updated 7 years ago
- ☆105Updated 5 years ago