Design of 4KB(1024*32) SRAM with operating voltage 1.8v and access time < 2.5ns
☆17Dec 8, 2020Updated 5 years ago
Alternatives and similar repositories for vsdsram_sky130
Users that are interested in vsdsram_sky130 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆42Feb 28, 2022Updated 4 years ago
- An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop…☆16Jul 22, 2020Updated 6 years ago
- Repository for VSD-IAT Workshop: Physical Verification using SKY130☆11Aug 15, 2021Updated 5 years ago
- This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—4…☆15Oct 18, 2021Updated 4 years ago
- ☆16May 11, 2022Updated 4 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆85Nov 26, 2020Updated 5 years ago
- ☆17Sep 19, 2022Updated 4 years ago
- SRAM☆24Sep 6, 2020Updated 6 years ago
- SRAM build space for SKY130 provided by SkyWater.☆26Oct 20, 2021Updated 4 years ago
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆18Oct 16, 2021Updated 4 years ago
- ☆39Jul 11, 2022Updated 4 years ago
- Various low power labs using sky130☆13Sep 3, 2021Updated 5 years ago
- This project has files needed to design and characterise flipflop☆21Jun 3, 2019Updated 7 years ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆126Jul 31, 2021Updated 5 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ☆49Apr 7, 2024Updated 2 years ago
- Two Stage CMOS Operational Amplifier IP Design using Skywater 130nm Technology☆27Jul 23, 2022Updated 4 years ago
- Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory…☆31Oct 18, 2018Updated 7 years ago
- Solve one design problem each day for a month☆56Feb 3, 2023Updated 3 years ago
- ☆13Apr 22, 2021Updated 5 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆56Jan 4, 2022Updated 4 years ago
- Test Chip General Purpose OpAmp using Skywater SKY130 PDK☆21Mar 1, 2021Updated 5 years ago
- # 3.Interview_Questions In my experience, the questions i faced in the interviews and the people surrounded me must have faced a couple o…☆26Jul 9, 2025Updated last year
- This repository contains source code that is aimed at converting a Spice NetList to its corresponding layout.☆28Mar 29, 2021Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆98Mar 19, 2026Updated 6 months ago
- A survey of manufacturer-provided DRAM operating parameters and timings as specified by DRAM chip datasheets from between 1970 and 2021. …☆11May 4, 2022Updated 4 years ago
- LibreSilicon's Standard Cell Library Generator☆22Aug 22, 2026Updated last month
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆91May 2, 2021Updated 5 years ago
- This project shows the design of two 4-bit current steering DACs, based on Binary and Segmented architectures at VDD=1.8V supply, using h…☆26May 2, 2025Updated last year
- 32-bit RISC-V microcontroller☆13Sep 11, 2021Updated 5 years ago
- Schematic, Layout Design & Simulation in 180nm Technology☆23Nov 21, 2020Updated 5 years ago
- AMC: Asynchronous Memory Compiler☆56Jun 29, 2020Updated 6 years ago
- This repository contains all the materials related to the basic MOSFET theory, CMOS technology, circuit and layout design, and basic PDK …☆15Dec 15, 2023Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- MD5 in VHDL☆11Jan 4, 2017Updated 9 years ago
- This is the Google/EFabless/Skywater Caravel submission of an Analog Spiking Neuron Circuit. The submission also includes a SONOS transis…☆12Apr 21, 2023Updated 3 years ago
- Verilog RTL Design☆53Sep 4, 2021Updated 5 years ago
- This repository will maintain simulation files, layout files and other relevant files on the SAR ADC worked on in the VSD Summer Online I…☆21Dec 15, 2020Updated 5 years ago
- Primitives for SKY130 provided by SkyWater.☆41Mar 9, 2024Updated 2 years ago
- ☆21Nov 22, 2021Updated 4 years ago
- Reusable 4-bit CPU in Logisim with Verilog HDL, ISA docs, and a browser playground☆14Feb 24, 2026Updated 7 months ago