Alternatives and similar repositories for CharLib

Users that are interested in CharLib are comparing it to the libraries listed below

• efabless / cace
  Circuit Automatic Characterization Engine
  ☆51Updated 7 months ago
• spider-tronix / Standard-Cell-Characterization
  Open Source tool to build liberty files and for Characterizing Standard Cells.
  ☆27Updated 4 years ago
• snishizawa / libretto
  Characterizer
  ☆30Updated last month
• johnkustin / bandgapReferenceCircuit
  repository for a bandgap voltage reference in SKY130 technology
  ☆40Updated 2 years ago
• vsdip / vsdStdCellCharacterizer_sky130
  ☆20Updated 3 years ago
• niftylab / laygo2
  LAYout with Gridded Objects v2
  ☆64Updated 3 months ago
• laurentc2 / SKY130_for_KLayout
  KLayout technology files for Skywater SKY130
  ☆42Updated 2 years ago
• mabrains / PLL_design
  PLL Designs on Skywater 130nm MPW
  ☆21Updated last year
• pulp-platform / artistic
  An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders
  ☆18Updated 2 months ago
• ALIGN-analoglayout / AnalogDetailedRouter
  Intel's Analog Detailed Router
  ☆39Updated 6 years ago
• pulp-platform / svase
  ☆32Updated 8 months ago
• StefanSchippers / xschem_sky130
  XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.
  ☆65Updated 3 weeks ago
• iic-jku / SKY130_SAR-ADC1
  Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license
  ☆47Updated 6 months ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆50Updated 5 months ago
• iic-jku / IIC-RALF
  Reinforcement learning assisted analog layout design flow.
  ☆29Updated last year
• ACMmodel / MOSFET_model
  A simple MOSFET model with only 5-DC-parameters for circuit simulation
  ☆49Updated 3 weeks ago
• sgherbst / sky130-hello-world
  Minimal SKY130 example with self-checking LVS, DRC, and PEX
  ☆23Updated 4 years ago
• dan-fritchman / Hdl21
  Hardware Description Library
  ☆84Updated 5 months ago
• bluecheetah / bag
  BAG framework
  ☆41Updated last year
• RTimothyEdwards / capiche
  Parasitic capacitance analysis of foundry metal stackups
  ☆15Updated 5 months ago
• magical-eda / MAGICAL-CIRCUITS
  Circuit release of the MAGICAL project
  ☆37Updated 5 years ago
• sscs-ose / sscs-chipathon-2024
  ☆84Updated 8 months ago
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆61Updated last year
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆51Updated 5 years ago
• fabianschuiki / potstill
  An open source generator for standard cell based memories.
  ☆14Updated 9 years ago
• AsFigo / yoYoLint
  SystemVerilog RTL Linter for YoSys
  ☆21Updated 10 months ago
• vsdip / vsdsram_sky130
  ☆43Updated 3 years ago
• nickson-jose / vsdstdcelldesign
  This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…
  ☆74Updated 4 years ago
• eskiyerli / revolution-eda
  This repository is for (pre-)release versions of the Revolution EDA.
  ☆43Updated this week
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated last year