Gate-level visualization generator for SKY130-based chip designs.
☆20Jul 22, 2021Updated 4 years ago
Alternatives and similar repositories for sky130-chip-vis
Users that are interested in sky130-chip-vis are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Cryptography accelerator core (for AES128/AES256 and SHA256) designed in Chisel3, primarily targeting ASIC platforms.☆10Jan 11, 2021Updated 5 years ago
- 32-bit RISC-V microcontroller☆12Sep 11, 2021Updated 4 years ago
- Translates GDSII into HTML/JS that can be viewed in WebGL-capable web browsers.☆59Aug 23, 2020Updated 5 years ago
- Project 1.1 Simulate a Skywater 130nm standard cell using ngspice☆14Jul 18, 2025Updated 10 months ago
- RISC-V CPU in SystemVerilog & Custom Migen-based SoC Generator☆10Dec 29, 2021Updated 4 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- Cryptography accelerator ASIC (for AES128/AES256 and SHA256) using Skywater 130nm process node (main project repo). Taped out in December…☆24Jan 13, 2021Updated 5 years ago
- LibreSilicon's Standard Cell Library Generator☆22Mar 27, 2026Updated last month
- 21st century electronic design automation tools, written in Rust.☆37May 7, 2026Updated 2 weeks ago
- A ritual to channel the unseen☆16Jan 15, 2025Updated last year
- This repository aims to capture the works done in 5-day workshop of Adavance Physical Design using OpenLANE/SkyWater130. The workshop hel…☆22Jul 5, 2021Updated 4 years ago
- ☆29Sep 3, 2025Updated 8 months ago
- A Python to VHDL compiler☆17Apr 28, 2025Updated last year
- ☆21Apr 8, 2019Updated 7 years ago
- System on Chip toolkit for Amaranth HDL☆101Mar 3, 2026Updated 2 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- ☆24Dec 8, 2021Updated 4 years ago
- XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.☆71May 13, 2026Updated last week
- Bluespec H.264 Decoder☆12Jul 17, 2014Updated 11 years ago
- An automatic clock gating utility☆53Apr 15, 2025Updated last year
- Symbolic differentation of algebraic expressions with Python and Tcl interfaces.☆19Oct 12, 2025Updated 7 months ago
- Testing Ibex build using Yosys and open source toolchains.☆11Oct 2, 2021Updated 4 years ago
- converts catgirls to gds files☆15May 24, 2021Updated 4 years ago
- WebAssembly-based Yosys distribution for Amaranth HDL☆29Apr 21, 2026Updated last month
- Converting systemverilog to verilog.☆10Feb 15, 2018Updated 8 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Standard Cell Library based Memory Compiler using FF/Latch cells☆167Nov 10, 2025Updated 6 months ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆36Apr 9, 2026Updated last month
- Copyleftist's Standard Cell Library☆102May 2, 2024Updated 2 years ago
- A configurable SRAM generator☆62May 15, 2026Updated last week
- Prefix tree adder space exploration library☆55Jan 27, 2026Updated 3 months ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆21Feb 25, 2023Updated 3 years ago
- download the macOS SDK legally without an Apple account☆12Jun 1, 2023Updated 2 years ago
- IO and periphery cells for the GF180MCU provided by GlobalFoundries.☆14Dec 3, 2022Updated 3 years ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆30Jan 21, 2025Updated last year
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Description of Apple's LEAP ISA☆16Nov 21, 2022Updated 3 years ago
- Logic circuit analysis and optimization☆49Feb 2, 2026Updated 3 months ago
- Some WIP GameCube toolchain in Rust☆13Jun 15, 2021Updated 4 years ago
- Mirror of tachyon-da cvc Verilog simulator☆54Mar 16, 2026Updated 2 months ago
- Rust Test Bench - write HDL tests in Rust.☆27Nov 28, 2022Updated 3 years ago
- Online RISC-V/MIPS Assembler & Simulator☆12Jul 18, 2022Updated 3 years ago
- This is the Google/EFabless/Skywater Caravel submission of an Analog Spiking Neuron Circuit. The submission also includes a SONOS transis…☆12Apr 21, 2023Updated 3 years ago