asinghani / sky130-chip-vis
Gate-level visualization generator for SKY130-based chip designs.
☆19Updated 3 years ago
Alternatives and similar repositories for sky130-chip-vis:
Users that are interested in sky130-chip-vis are comparing it to the libraries listed below
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- ☆36Updated 2 years ago
- An automatic clock gating utility☆45Updated 8 months ago
- AXI Formal Verification IP☆20Updated 3 years ago
- ☆33Updated 2 years ago
- A padring generator for ASICs☆25Updated last year
- Project 1.1 Simulate a Skywater 130nm standard cell using ngspice☆13Updated 11 months ago
- Index of the fully open source process design kits (PDKs) maintained by Google for GlobalFoundries technologies.☆48Updated 2 years ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆27Updated 2 months ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆28Updated 8 months ago
- Specification of the Wishbone SoC Interconnect Architecture☆44Updated 2 years ago
- An open source PDK using TIGFET 10nm devices.☆48Updated 2 years ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- Virtual development board for HDL design☆41Updated last year
- ☆39Updated 2 years ago
- USB virtual model in C++ for Verilog☆29Updated 5 months ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆40Updated 3 months ago
- ☆31Updated last year
- A Python package for generating HDL wrappers and top modules for HDL sources☆32Updated last week
- A current mode buck converter on the SKY130 PDK☆27Updated 3 years ago
- Benchmarks for Yosys development☆23Updated 5 years ago
- ☆15Updated 4 months ago
- Characterizer☆21Updated 7 months ago
- Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130☆4Updated 4 months ago
- ☆31Updated 2 months ago
- KLayout technology files for ASAP7 FinFET educational process☆20Updated 2 years ago
- LibreSilicon's Standard Cell Library Generator☆18Updated 10 months ago
- A configurable SRAM generator☆47Updated 2 months ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆41Updated last year
- PicoRV☆44Updated 5 years ago