Alternatives and similar repositories for sky130-chip-vis

Users that are interested in sky130-chip-vis are comparing it to the libraries listed below

• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆51Updated 6 months ago
• dbhi / vboard
  Virtual development board for HDL design
  ☆42Updated 2 years ago
• tdene / synth_opt_adders
  Prefix tree adder space exploration library
  ☆56Updated 11 months ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆118Updated 2 years ago
• dh73 / A_Formal_Tale_Chapter_I_AMBA
  AXI Formal Verification IP
  ☆20Updated 4 years ago
• iic-jku / SKY130_SAR-ADC1
  Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license
  ☆48Updated 7 months ago
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆47Updated 3 months ago
• AL-255 / Project-Yatsuhashi-Chip1
  ☆38Updated 2 years ago
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated last year
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆48Updated 3 years ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆51Updated 2 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• b224hisl / rioschip
  ☆32Updated 2 years ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆38Updated last week
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆48Updated 2 years ago
• efabless / caravel_mgmt_soc_litex
  https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/
  ☆28Updated 9 months ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 6 months ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆43Updated 2 years ago
• themperek / spicebind
  SpiceBind – spice inside HDL simulator
  ☆56Updated 4 months ago
• openecos-projects / icsprout55-pdk
  55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.
  ☆91Updated this week
• efabless / caravel-lite
  ☆17Updated last year
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆86Updated 5 years ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• FPGA-Research / FABulator
  Fabric generator and CAD tools graphical frontend
  ☆17Updated 3 months ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆32Updated last year
• pulp-platform / cheshire-ihp130-o
  ☆58Updated 7 months ago
• google / globalfoundries-pdks
  Index of the fully open source process design kits (PDKs) maintained by Google for GlobalFoundries technologies.
  ☆49Updated 3 years ago