asinghani / sky130-chip-visLinks
Gate-level visualization generator for SKY130-based chip designs.
☆19Updated 3 years ago
Alternatives and similar repositories for sky130-chip-vis
Users that are interested in sky130-chip-vis are comparing it to the libraries listed below
Sorting:
- ☆36Updated 2 years ago
- An automatic clock gating utility☆47Updated last month
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- AXI Formal Verification IP☆20Updated 4 years ago
- Characterizer☆22Updated 2 weeks ago
- An open source PDK using TIGFET 10nm devices.☆48Updated 2 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- ☆39Updated 2 years ago
- Bitstream relocation and manipulation tool.☆45Updated 2 years ago
- Project 1.1 Simulate a Skywater 130nm standard cell using ngspice☆14Updated this week
- Prefix tree adder space exploration library☆57Updated 6 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆33Updated 2 weeks ago
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆27Updated 4 months ago
- LunaPnR is a place and router for integrated circuits☆46Updated 6 months ago
- Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130☆6Updated last week
- ☆33Updated 2 years ago
- USB virtual model in C++ for Verilog☆30Updated 7 months ago
- ☆32Updated 4 months ago
- ☆44Updated 2 months ago
- A configurable SRAM generator☆50Updated last week
- Analog and power building blocks for sky130 pdk☆20Updated 4 years ago
- ☆22Updated 3 weeks ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆41Updated 2 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆30Updated 4 years ago
- ☆35Updated 6 months ago
- ☆46Updated 3 months ago
- FPGA250 aboard the eFabless Caravel☆29Updated 4 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆29Updated 10 months ago