efabless / caravel_mgmt_soc_litexLinks
https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/
☆28Updated 7 months ago
Alternatives and similar repositories for caravel_mgmt_soc_litex
Users that are interested in caravel_mgmt_soc_litex are comparing it to the libraries listed below
Sorting:
- ☆38Updated 3 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- ☆17Updated 9 months ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- ☆22Updated last month
- ☆14Updated 3 years ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 8 months ago
- An open source PDK using TIGFET 10nm devices.☆49Updated 2 years ago
- Guides and templates for using open source RF design tools with the SkyWater SKY130 process.☆19Updated 4 years ago
- Analog and power building blocks for sky130 pdk☆20Updated 4 years ago
- ☆12Updated 3 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆42Updated 5 months ago
- ☆20Updated 3 years ago
- Characterizer☆30Updated 2 weeks ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- ☆42Updated 3 years ago
- Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/☆55Updated 4 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆117Updated last year
- Flip flop setup, hold & metastability explorer tool☆46Updated 2 years ago
- ☆42Updated 6 months ago
- Gate-level visualization generator for SKY130-based chip designs.☆21Updated 4 years ago
- Peripheral Component Interconnect has taken Express lane long ago, going for xGbps SerDes. Now (for the first time) in opensource on the …☆16Updated this week
- Extended and external tests for Verilator testing☆16Updated 3 weeks ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆35Updated 2 weeks ago
- ☆36Updated 9 months ago
- Yosys plugin for logic locking and supply-chain security☆22Updated 4 months ago
- ☆32Updated 7 months ago
- LunaPnR is a place and router for integrated circuits☆47Updated last month
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆31Updated 4 years ago