efabless / caravel_mgmt_soc_litex
https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/
☆26Updated last month
Alternatives and similar repositories for caravel_mgmt_soc_litex:
Users that are interested in caravel_mgmt_soc_litex are comparing it to the libraries listed below
- ☆36Updated 2 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- ☆45Updated last month
- submission repository for efabless mpw6 shuttle☆30Updated last year
- ☆19Updated last year
- ☆15Updated 2 months ago
- An automatic clock gating utility☆43Updated 6 months ago
- ☆31Updated last week
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆42Updated 4 years ago
- ☆40Updated 2 years ago
- PLL Designs on Skywater 130nm MPW☆20Updated last year
- Index of the fully open source process design kits (PDKs) maintained by Google for GlobalFoundries technologies.☆47Updated 2 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆35Updated 3 years ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆14Updated 4 years ago
- ☆12Updated 2 years ago
- ☆14Updated 3 years ago
- Skywater 130nm Klayout Device Generators PDK☆29Updated 6 months ago
- JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.☆56Updated 2 months ago
- ☆32Updated 2 months ago
- ☆36Updated 3 months ago
- ☆20Updated 3 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆64Updated 4 years ago
- XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.☆59Updated this week
- Open source process design kit for 28nm open process☆46Updated 8 months ago
- Parasitic capacitance analysis of foundry metal stackups☆10Updated 4 months ago
- Plugins for Yosys developed as part of the F4PGA project.☆80Updated 8 months ago
- This repository in a walk through the entire process of PLL IC designing from the tools to the final tapeout.☆19Updated 2 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆40Updated 3 years ago
- Flip flop setup, hold & metastability explorer tool☆32Updated 2 years ago
- ☆33Updated 2 years ago