mattvenn / logo-to-gds2

Related projects ⓘ

Alternatives and complementary repositories for logo-to-gds2

• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆20Updated 3 years ago
• htfab / rotfpga
  A reconfigurable logic circuit made of identical rotatable tiles.
  ☆19Updated 2 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆50Updated last year
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆43Updated 3 months ago
• wulffern / tt06-sar
  SAR ADC on tiny tapeout
  ☆31Updated this week
• YosysHQ / padring
  A padring generator for ASICs
  ☆22Updated last year
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆28Updated 3 weeks ago
• wavedrom / vcd-samples
  sample VCD files
  ☆36Updated 8 months ago
• hdl / constraints
  Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
  ☆42Updated this week
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• westonb / open-pmic
  A current mode buck converter on the SKY130 PDK
  ☆26Updated 3 years ago
• mattvenn / magic-inverter
  an inverter drawn in magic with makefile to simulate
  ☆26Updated 2 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated last year
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆54Updated last month
• hdl / symbolator
  Generate symbols from HDL components/modules
  ☆20Updated last year
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆36Updated 3 years ago
• mattvenn / simulate-gate
  Project 1.1 Simulate a Skywater 130nm standard cell using ngspice
  ☆12Updated 6 months ago
• efabless / caravel_mgmt_soc_litex
  https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/
  ☆26Updated 3 weeks ago
• efabless / caravel-lite
  ☆15Updated this week
• google / globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0
  9 track standard cells for GF180MCU provided by GlobalFoundries.
  ☆16Updated last year
• www-asics-ws / usb1_device
  USB 1.1 Device IP Core
  ☆18Updated 7 years ago
• semify-eda / fstdumper
  Verilog VPI module to dump FST (Fast Signal Trace) databases
  ☆16Updated last year
• samlittlewood / caravel_carrier
  Carrier for efabless Caravel chip used for Google/Skywater 130nm shuttle program.
  ☆18Updated 3 years ago
• eskiyerli / revedaRelease
  This repository is for (pre-)release versions of the Revolution EDA.
  ☆35Updated this week
• RTimothyEdwards / capiche
  Parasitic capacitance analysis of foundry metal stackups
  ☆10Updated last month
• jazvw / chip_art
  Convert an image to a GDS format for inclusion in a zerotoasic project
  ☆13Updated 2 years ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆31Updated 2 years ago
• grayresearch / s4ga
  a small simple slow serial FPGA core
  ☆16Updated 3 years ago
• mattvenn / flipflop_demo
  Flip flop setup, hold & metastability explorer tool
  ☆31Updated 2 years ago
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆40Updated 3 years ago