mattvenn / logo-to-gds2
☆18Updated 2 years ago
Alternatives and similar repositories for logo-to-gds2:
Users that are interested in logo-to-gds2 are comparing it to the libraries listed below
- Gate-level visualization generator for SKY130-based chip designs.☆19Updated 3 years ago
- KLayout technology files for ASAP7 FinFET educational process☆20Updated 2 years ago
- A padring generator for ASICs☆25Updated last year
- Generate symbols from HDL components/modules☆21Updated 2 years ago
- ☆36Updated 2 years ago
- An automatic clock gating utility☆47Updated last week
- A reconfigurable logic circuit made of identical rotatable tiles.☆21Updated 3 years ago
- USB virtual model in C++ for Verilog☆29Updated 6 months ago
- LunaPnR is a place and router for integrated circuits☆46Updated 5 months ago
- An open source PDK using TIGFET 10nm devices.☆48Updated 2 years ago
- CMake based hardware build system☆16Updated last week
- A current mode buck converter on the SKY130 PDK☆27Updated 3 years ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆27Updated 3 months ago
- Cross EDA Abstraction and Automation☆36Updated last week
- Small footprint and configurable Inter-Chip communication cores☆57Updated this week
- submission repository for efabless mpw6 shuttle☆30Updated last year
- Convert an image to a GDS format for inclusion in a zerotoasic project☆13Updated 2 years ago
- SAR ADC on tiny tapeout☆38Updated 2 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- Characterizer☆22Updated 8 months ago
- 9 track standard cells for GF180MCU provided by GlobalFoundries.☆16Updated 2 years ago
- LibreSilicon's Standard Cell Library Generator☆18Updated 11 months ago
- Digital Circuit rendering engine☆38Updated last year
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- IRSIM switch-level simulator for digital circuits☆32Updated 2 weeks ago
- ☆10Updated last year
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆29Updated 9 months ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆44Updated last week