mattvenn / logo-to-gds2
☆16Updated last year
Related projects ⓘ
Alternatives and complementary repositories for logo-to-gds2
- LunaPnR is a place and router for integrated circuits☆44Updated this week
- A reconfigurable logic circuit made of identical rotatable tiles.☆20Updated 3 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆20Updated 3 years ago
- A padring generator for ASICs☆22Updated last year
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆31Updated 2 years ago
- Small footprint and configurable Inter-Chip communication cores☆54Updated last month
- ☆36Updated 2 years ago
- ☆15Updated 2 weeks ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆42Updated this week
- sample VCD files☆36Updated 9 months ago
- Generate symbols from HDL components/modules☆20Updated last year
- A current mode buck converter on the SKY130 PDK☆26Updated 3 years ago
- USB virtual model in C++ for Verilog☆28Updated last month
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆26Updated last month
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- 9 track standard cells for GF180MCU provided by GlobalFoundries.☆16Updated last year
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year
- USB 1.1 Device IP Core☆18Updated 7 years ago
- Analog and power building blocks for sky130 pdk☆20Updated 3 years ago
- Verilog Modules and Python Scripts for Creating IP Core Build Directories☆29Updated last year
- Examples and design pattern for VHDL verification☆15Updated 8 years ago
- An open source PDK using TIGFET 10nm devices.☆43Updated last year
- Using VexRiscv without installing Scala☆36Updated 3 years ago
- Set up your GitHub Actions workflow with a OSS CAD Suite☆14Updated 8 months ago
- KLayout technology files for ASAP7 FinFET educational process☆18Updated last year
- submission repository for efabless mpw6 shuttle☆30Updated 10 months ago
- Verilog based simulation modell for 7 Series PLL☆12Updated 4 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated last year
- Index of the fully open source process design kits (PDKs) maintained by Google for GlobalFoundries technologies.☆46Updated 2 years ago
- Library of reusable VHDL components☆25Updated 8 months ago