vsdip / vsdStdCellCharacterizer_sky130
☆20Updated 3 years ago
Alternatives and similar repositories for vsdStdCellCharacterizer_sky130:
Users that are interested in vsdStdCellCharacterizer_sky130 are comparing it to the libraries listed below
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆23Updated 4 years ago
- SystemVerilog RTL Linter for YoSys☆19Updated 2 months ago
- Automatic generation of real number models from analog circuits☆37Updated 10 months ago
- ☆40Updated 5 years ago
- ☆40Updated 2 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆42Updated 4 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- Design of Analog Blocks in Skywaters 130nm meeting corners: different flavors of OTA, BandGap, LDO.☆26Updated 2 years ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆24Updated 4 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆43Updated 3 years ago
- AMC: Asynchronous Memory Compiler☆48Updated 4 years ago
- Design of 4KB(1024*32) SRAM with operating voltage 1.8v and access time < 2.5ns☆12Updated 4 years ago
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆39Updated 6 months ago
- Open Source PHY v2☆25Updated 9 months ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆27Updated 3 years ago
- Open-source repository for a standard-cell library characterizer using complete open-source tools☆24Updated 2 weeks ago
- PLL Designs on Skywater 130nm MPW☆20Updated last year
- An open source PDK using TIGFET 10nm devices.☆47Updated 2 years ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 4 years ago
- LibreSilicon's Standard Cell Library Generator☆18Updated 9 months ago
- SRAM☆8Updated 4 years ago
- BAG framework☆40Updated 6 months ago
- ☆12Updated 2 years ago
- ☆32Updated 5 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆64Updated 4 years ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆22Updated last month
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆39Updated last year
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆21Updated 6 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆35Updated 2 years ago