☆26Apr 24, 2021Updated 5 years ago
Alternatives and similar repositories for librecell
Users that are interested in librecell are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆19Jul 22, 2020Updated 5 years ago
- ASTRAN - Automatic Synthesis of Transistor Networks☆66Apr 4, 2022Updated 4 years ago
- AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining☆18Nov 1, 2022Updated 3 years ago
- Cell Layout Generation for DTCO/STCO Exploration Toolkit☆24May 24, 2025Updated 11 months ago
- iverilog extension for Visual Studio Code to satisfy the needs for an easy testbench runner. Includes builtin GTKWave support.☆11Mar 4, 2023Updated 3 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- LibreSilicon's Standard Cell Library Generator☆22Mar 27, 2026Updated last month
- ☆56Apr 8, 2024Updated 2 years ago
- ☆17May 18, 2024Updated last year
- This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".☆25Jul 12, 2023Updated 2 years ago
- Characterizer☆35Nov 19, 2025Updated 5 months ago
- ☆21Oct 5, 2024Updated last year
- Parametric layout generator for digital, analog and mixed-signal integrated circuits☆74Apr 23, 2026Updated last week
- ☆33May 8, 2025Updated 11 months ago
- UCSD Detailed Router☆98Jan 5, 2021Updated 5 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Macro Placement - benchmarks, evaluators, and reproducible results from leading methods in open source☆332Jan 5, 2026Updated 3 months ago
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆27Apr 9, 2025Updated last year
- Coriolis VLSI EDA Tool (LIP6)☆84Apr 20, 2026Updated last week
- This is a deep-learning based model for Electronic Design Automation(EDA), predicting the Design Rule Check (DRC) violation location.☆13Jun 24, 2023Updated 2 years ago
- Copyleftist's Standard Cell Library☆102May 2, 2024Updated last year
- Primitives for GF180MCU provided by GlobalFoundries.☆12Jul 6, 2025Updated 9 months ago
- ☆46Mar 2, 2023Updated 3 years ago
- Delay Calculation ToolKit☆32Aug 7, 2022Updated 3 years ago
- tools regarding on analog modeling, validation, and generation☆22Apr 11, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆25Nov 7, 2024Updated last year
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆44May 29, 2025Updated 11 months ago
- Code for PyMTL Tutorial @ ISCA 2019☆11Jun 22, 2019Updated 6 years ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆28Feb 18, 2021Updated 5 years ago
- ☆31Apr 23, 2024Updated 2 years ago
- Intel's Analog Detailed Router☆42Jul 18, 2019Updated 6 years ago
- Fully defined liberty (std. cells in VLSI) data structure, efficient parser & formatter☆25Feb 24, 2026Updated 2 months ago
- ☆355Updated this week
- 21st century electronic design automation tools, written in Rust.☆36Apr 16, 2026Updated 2 weeks ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Open Source Detailed Placement engine☆13Feb 19, 2020Updated 6 years ago
- An out-of-order, dual issueed RISC-V core and SOC, a working project.☆10Apr 24, 2023Updated 3 years ago
- UCSD Sizer for leakage/dynamic power recovery, timing recovery☆18Mar 5, 2019Updated 7 years ago
- CUGR, VLSI Global Routing Tool Developed by CUHK☆145Feb 27, 2023Updated 3 years ago
- GDSII File Parsing, IC Layout Analysis, and Parameter Extraction☆130Apr 23, 2023Updated 3 years ago
- ☆45May 18, 2024Updated last year
- ☆12Feb 15, 2024Updated 2 years ago