☆27Apr 24, 2021Updated 5 years ago
Alternatives and similar repositories for librecell
Users that are interested in librecell are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆20Jul 22, 2020Updated 6 years ago
- ☆15Mar 22, 2022Updated 4 years ago
- ASTRAN - Automatic Synthesis of Transistor Networks☆67Apr 4, 2022Updated 4 years ago
- AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining☆20Nov 1, 2022Updated 3 years ago
- Cell layout generation (MH Multiheight) for DTCO/STCO exploration toolkit.☆15Oct 6, 2025Updated 10 months ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- ☆58Apr 8, 2024Updated 2 years ago
- Cell Layout Generation for DTCO/STCO Exploration Toolkit☆32May 24, 2025Updated last year
- LibreSilicon's Standard Cell Library Generator☆22Jun 7, 2026Updated 2 months ago
- iverilog extension for Visual Studio Code to satisfy the needs for an easy testbench runner. Includes builtin GTKWave support.☆11Mar 4, 2023Updated 3 years ago
- ☆16May 18, 2024Updated 2 years ago
- This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".☆28Jul 12, 2023Updated 3 years ago
- Characterizer☆39Jun 26, 2026Updated last month
- ☆22Oct 5, 2024Updated last year
- UCSD Detailed Router☆98Jan 5, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Macro Placement - benchmarks, evaluators, and reproducible results from leading methods in open source☆343Jan 5, 2026Updated 7 months ago
- Fully defined liberty (std. cells in VLSI) data structure, efficient parser & formatter☆27Feb 24, 2026Updated 5 months ago
- Parametric layout generator for digital, analog and mixed-signal integrated circuits☆81Jul 28, 2026Updated last week
- This is a deep-learning based model for Electronic Design Automation(EDA), predicting the Design Rule Check (DRC) violation location.☆13Jun 24, 2023Updated 3 years ago
- Copyleftist's Standard Cell Library☆105May 2, 2024Updated 2 years ago
- Coriolis VLSI EDA Tool (LIP6)☆91Updated this week
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆29Feb 18, 2021Updated 5 years ago
- Primitives for GF180MCU provided by GlobalFoundries.☆13Jul 6, 2025Updated last year
- Delay Calculation ToolKit☆32Aug 7, 2022Updated 4 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ☆26Nov 7, 2024Updated last year
- Code for PyMTL Tutorial @ ISCA 2019☆11Jun 22, 2019Updated 7 years ago
- tools regarding on analog modeling, validation, and generation☆25Apr 11, 2023Updated 3 years ago
- ☆41May 8, 2025Updated last year
- Intel's Analog Detailed Router☆43Jul 18, 2019Updated 7 years ago
- ☆377Updated this week
- ☆31Apr 23, 2024Updated 2 years ago
- 21st century electronic design automation tools, written in Rust.☆37Updated this week
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆29Apr 9, 2025Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆16Feb 5, 2026Updated 6 months ago
- CUGR, VLSI Global Routing Tool Developed by CUHK☆153Feb 27, 2023Updated 3 years ago
- Open Source Detailed Placement engine☆13Feb 19, 2020Updated 6 years ago
- GDSII File Parsing, IC Layout Analysis, and Parameter Extraction☆136Apr 23, 2023Updated 3 years ago
- UCSD Sizer for leakage/dynamic power recovery, timing recovery☆18Mar 5, 2019Updated 7 years ago
- Parser and Viewer for Cadence® Library Exchange Format (LEF) and Design Exchange Format (DEF) integrated circuit (IC) description languag…☆17May 31, 2023Updated 3 years ago
- Computer architecture project : Cache simulator with LRU replacement policy☆12Jul 27, 2021Updated 5 years ago