YosysHQ / yosys-bigsimLinks
A collection of big designs to run post-synthesis simulations with yosys
☆51Updated 10 years ago
Alternatives and similar repositories for yosys-bigsim
Users that are interested in yosys-bigsim are comparing it to the libraries listed below
Sorting:
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Benchmarks for Yosys development☆24Updated 5 years ago
- ☆38Updated 3 years ago
- Mutation Cover with Yosys (MCY)☆89Updated 3 weeks ago
- Collection of test cases for Yosys☆17Updated 3 years ago
- Builds, flow and designs for the alpha release☆54Updated 6 years ago
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- FPGA tool performance profiling☆104Updated last year
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- Facilitates building open source tools for working with hardware description languages (HDLs)☆66Updated 6 years ago
- An automatic clock gating utility☆51Updated 8 months ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- ☆59Updated 3 years ago
- A library and command-line tool for querying a Verilog netlist.☆29Updated 3 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 5 months ago
- Bitstream relocation and manipulation tool.☆50Updated 3 years ago
- Demo SoC for SiliconCompiler.☆62Updated last week
- A SystemVerilog source file pickler.☆60Updated last year
- RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA☆90Updated 5 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆44Updated 2 years ago
- Mathematical Functions in Verilog☆95Updated 4 years ago
- For contributions of Chisel IP to the chisel community.☆69Updated last year
- ☆44Updated 5 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆89Updated last year
- SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research☆38Updated last year
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆66Updated 3 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 5 months ago