A collection of big designs to run post-synthesis simulations with yosys
☆51Oct 27, 2015Updated 10 years ago
Alternatives and similar repositories for yosys-bigsim
Users that are interested in yosys-bigsim are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- GUI for SymbiYosys☆17Oct 13, 2025Updated 5 months ago
- Collection of test cases for Yosys☆17Jan 4, 2022Updated 4 years ago
- Yosys Plugins☆22Jul 16, 2019Updated 6 years ago
- Benchmarks for Yosys development☆24Feb 17, 2020Updated 6 years ago
- Provides a packaged collection of open source EDA tools☆12Apr 14, 2019Updated 6 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- LibreSilicon's Standard Cell Library Generator☆22Oct 30, 2025Updated 4 months ago
- ☆13Mar 18, 2026Updated last week
- A Verilog Synthesis Regression Test☆37Jan 19, 2026Updated 2 months ago
- Verilog hardware abstraction library☆50Mar 22, 2026Updated last week
- Project Trellis database☆14Sep 15, 2025Updated 6 months ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆32Mar 9, 2026Updated 2 weeks ago
- Optimal gate sizing of digital circuits using geometric programming☆11Aug 18, 2016Updated 9 years ago
- Tool to fetch and parse data about Efabless MPW projects☆15Jan 10, 2023Updated 3 years ago
- OpenDesign Flow Database☆17Oct 31, 2018Updated 7 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Tools and Examples for IcoBoard☆80Jul 13, 2021Updated 4 years ago
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆500Updated this week
- SMT-based-STDCELL-Layout-Generator☆18Sep 30, 2021Updated 4 years ago
- Icestorm, Arachne-pnr and Yosys pre-built binaries: GNU/Linux(+ARM), Windows and Mac OS☆39May 9, 2022Updated 3 years ago
- ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.☆17Dec 1, 2018Updated 7 years ago
- 9 track standard cells for GF180MCU provided by GlobalFoundries.☆18Dec 5, 2022Updated 3 years ago
- C# projects that use ANTLR4 library to analyse VHDL and Verilog code☆11Feb 28, 2015Updated 11 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆15Nov 9, 2014Updated 11 years ago
- ☆33Jul 28, 2020Updated 5 years ago
- Wordpress hosting with auto-scaling on Cloudways • AdFully Managed hosting built for WordPress-powered businesses that need reliable, auto-scalable hosting. Cloudways SafeUpdates now available.
- A padring generator for ASICs☆26May 17, 2023Updated 2 years ago
- DATC Robust Design Flow.☆35Jan 21, 2020Updated 6 years ago
- verilog core for ws2812 leds☆35Nov 3, 2021Updated 4 years ago
- ☆44Jan 26, 2020Updated 6 years ago
- Equivalence checking with Yosys☆58Mar 19, 2026Updated last week
- IDEA project source files☆112Oct 15, 2025Updated 5 months ago
- a simple C-to-Verilog compiler☆51Apr 16, 2017Updated 8 years ago
- 55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.☆182Feb 28, 2026Updated last month
- Yosys Open SYnthesis Suite☆4,366Updated this week
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- The official website of One Student One Chip project.☆11Feb 5, 2026Updated last month
- ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set☆21Dec 23, 2024Updated last year
- A collection of SPI related cores☆21Nov 12, 2024Updated last year
- Integer Multiplier Generator for Verilog☆24Jul 4, 2025Updated 8 months ago
- This repository includes the data and scripts utilized in the study titled "Improving LLM-based Verilog Code Generation with Data Augment…☆14Mar 24, 2025Updated last year
- ☆97Jun 26, 2019Updated 6 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆33May 17, 2020Updated 5 years ago