YosysHQ / yosys-bigsim
A collection of big designs to run post-synthesis simulations with yosys
☆47Updated 8 years ago
Related projects: ⓘ
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆28Updated 2 months ago
- ☆28Updated 4 years ago
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- Collection of test cases for Yosys☆17Updated 2 years ago
- ☆35Updated 2 years ago
- Benchmarks for Yosys development☆21Updated 4 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆38Updated last year
- Source codes and calibration scripts for clock tree synthesis☆38Updated 4 years ago
- ☆37Updated 4 years ago
- An automatic clock gating utility☆40Updated 2 months ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆74Updated 3 weeks ago
- Mutation Cover with Yosys (MCY)☆76Updated 2 weeks ago
- SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research☆37Updated 3 weeks ago
- ☆30Updated 11 months ago
- 👾 Design ∪ Hardware☆72Updated 11 months ago
- AMC: Asynchronous Memory Compiler☆44Updated 4 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆66Updated 4 months ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆31Updated 2 months ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 2 years ago
- Builds, flow and designs for the alpha release☆53Updated 4 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆80Updated 3 years ago
- ☆51Updated 2 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆56Updated 3 years ago
- A Verilog Synthesis Regression Test☆33Updated 5 months ago
- OpenSoC Fabric - A Network-On-Chip Generator☆17Updated 7 years ago
- SCARV: a side-channel hardened RISC-V platform☆24Updated last year
- Plugins for Yosys developed as part of the F4PGA project.☆84Updated 4 months ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 4 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆45Updated 2 months ago
- For contributions of Chisel IP to the chisel community.☆55Updated 7 months ago