Alternatives and similar repositories for yosys-bigsim:

Users that are interested in yosys-bigsim are comparing it to the libraries listed below

• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆80Updated this week
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆29Updated 9 months ago
• The-OpenROAD-Project / TritonCTS
  Source codes and calibration scripts for clock tree synthesis
  ☆40Updated 5 years ago
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆18Updated 3 years ago
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 5 years ago
• mrc-donato / CHIPKIT-Tutorial
  ☆15Updated 4 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆47Updated 3 weeks ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated 11 months ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆27Updated 4 years ago
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆33Updated 9 months ago
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆55Updated last year
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆41Updated 2 years ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆48Updated 2 years ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆41Updated 4 years ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆48Updated 3 months ago
• woset-workshop / woset-workshop.github.io
  Workshop on Open-Source EDA Technology (WOSET)
  ☆49Updated 5 months ago
• aolofsson / POSH
  ☆44Updated 5 years ago
• idea-fasoc / fasoc
  ☆54Updated last year
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆36Updated 2 years ago
• SymbiFlow / vtr-verilog-to-routing
  SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆37Updated 8 months ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆29Updated 8 years ago
• bluecheetah / bag
  BAG framework
  ☆40Updated 9 months ago
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆57Updated 3 weeks ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆62Updated 11 months ago
• ucb-bar / barstools
  Useful utilities for BAR projects
  ☆31Updated last year