Alternatives and similar repositories for caravel_fpga250:

Users that are interested in caravel_fpga250 are comparing it to the libraries listed below

• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated 2 years ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆43Updated 6 months ago
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 2 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆37Updated 3 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated 8 months ago
• aignacio / mpsoc_example
  ☆59Updated 3 years ago
• FPGA-Research / eFPGA---RTL-to-GDS-with-SKY130
  This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
  ☆27Updated 3 years ago
• AL-255 / Project-Yatsuhashi-Chip1
  ☆39Updated 2 years ago
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆19Updated 3 years ago
• mattvenn / magic-inverter
  an inverter drawn in magic with makefile to simulate
  ☆26Updated 2 years ago
• clairexen / picorv
  PicoRV
  ☆44Updated 4 years ago
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆18Updated 2 months ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆39Updated last year
• dh73 / A_Formal_Tale_Chapter_I_AMBA
  AXI Formal Verification IP
  ☆20Updated 3 years ago
• pulp-platform / svase
  ☆31Updated 3 weeks ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆30Updated this week
• SymbioticEDA / getting-started-FV
  ☆18Updated 4 years ago
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆45Updated 2 months ago
• sifive / duh
  👾 Design ∪ Hardware
  ☆73Updated 2 months ago
• manili / VSDBabySoC
  VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.
  ☆36Updated 3 years ago
• efabless / caravel_user_project_analog
  ☆45Updated last month
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆50Updated last year
• wulffern / tt06-sar
  SAR ADC on tiny tapeout
  ☆37Updated 2 months ago
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆86Updated 5 years ago
• vsdip / vsdsram_sky130
  ☆40Updated 2 years ago
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆31Updated 6 months ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆38Updated last month
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆38Updated 8 months ago