ucb-cs250 / caravel_fpga250
FPGA250 aboard the eFabless Caravel
☆27Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for caravel_fpga250
- ☆36Updated 2 years ago
- Bitstream relocation and manipulation tool.☆40Updated last year
- Quick'n'dirty FuseSoC+cocotb example☆17Updated 5 months ago
- ☆33Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆67Updated 6 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated last year
- LunaPnR is a place and router for integrated circuits☆44Updated this week
- A padring generator for ASICs☆22Updated last year
- An automatic clock gating utility☆43Updated 4 months ago
- Using VexRiscv without installing Scala☆36Updated 3 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆64Updated 2 months ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆35Updated last year
- ☆57Updated 3 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆30Updated 3 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆30Updated last year
- ☆29Updated 2 months ago
- ☆39Updated 4 years ago
- A pipelined RISC-V processor☆47Updated 11 months ago
- A compact, configurable RISC-V core☆11Updated last week
- A Python package for generating HDL wrappers and top modules for HDL sources☆23Updated last week
- 👾 Design ∪ Hardware☆72Updated 2 weeks ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆39Updated last year
- Flip flop setup, hold & metastability explorer tool☆31Updated 2 years ago
- submission repository for efabless mpw6 shuttle☆30Updated 10 months ago
- ☆31Updated last week
- RISC-V Nox core☆61Updated 3 months ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆31Updated 4 months ago
- ☆18Updated 4 years ago
- ☆26Updated 3 years ago
- Python interface to FPGA interchange format☆41Updated 2 years ago