vsdip / vsdsramLinks
An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop) to store each bit. The size of SRAM specs is 32kbit/4k bytes with 1.8v. A 6T SRAM pairs up with two access transistors for read, write state and cross coupled inverter to hold/regenerate the state.
☆14Updated 5 years ago
Alternatives and similar repositories for vsdsram
Users that are interested in vsdsram are comparing it to the libraries listed below
Sorting:
- Design of 4KB Static RAM 1.8V (access time <2.5ns) using OpenRAM and Sky130 node☆14Updated 4 years ago
- LibreSilicon's Standard Cell Library Generator☆22Updated 3 months ago
- Design of 4KB(1024*32) SRAM with operating voltage 1.8v and access time < 2.5ns☆14Updated 5 years ago
- AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...☆13Updated 10 months ago
- ☆20Updated 4 years ago
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆24Updated 5 years ago
- ☆17Updated last year
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 5 years ago
- An open source PDK using TIGFET 10nm devices.☆56Updated 3 years ago
- ☆19Updated last year
- A RRAM addon for the NCSU FreePDK 45nm☆25Updated 4 years ago
- Extended and external tests for Verilator testing☆17Updated 2 weeks ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆33Updated last month
- MathLib DAC 2023 version☆13Updated 2 years ago
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆28Updated 6 years ago
- ☆41Updated 3 years ago
- SRAM☆22Updated 5 years ago
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆24Updated 5 years ago
- SystemC to Verilog Synthesizable Subset Translator☆12Updated 2 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆37Updated 3 years ago
- Analog and power building blocks for sky130 pdk☆22Updated 4 years ago
- ☆17Updated 3 years ago
- Pipelined FFT/IFFT 64 points processor☆11Updated 11 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆38Updated 4 years ago
- CMake based hardware build system☆35Updated last week
- ☆38Updated 3 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 5 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆44Updated 2 years ago
- Open source process design kit for 28nm open process☆72Updated last year