MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)
☆22Apr 17, 2024Updated 2 years ago
Alternatives and similar repositories for MaxEVA
Users that are interested in MaxEVA are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A compiler for lowering quantized ML models to AMD AI Engine (AIE) firmware.☆20Updated this week
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆174Mar 12, 2026Updated 4 months ago
- Generate versal system design from ONNX model. AI engine kernels. Sub-microsecond speeds for autoencoders.☆20Dec 29, 2024Updated last year
- Hands-on experience programming AI Engines using Vitis Unified Software Platform☆42Jul 24, 2024Updated 2 years ago
- Xilinx Modifications to Halide☆13May 3, 2021Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆25Jun 14, 2026Updated last month
- ☆11Sep 3, 2022Updated 3 years ago
- ☆13Jun 4, 2024Updated 2 years ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆37Mar 12, 2026Updated 4 months ago
- An MLIR-based compiler from C/C++ to AMD-Xilinx Versal AIE☆17Aug 5, 2022Updated 3 years ago
- Python functions and scripts to analyse cyclostationary signals☆26Feb 14, 2023Updated 3 years ago
- Reconfigurable Stream Network Architecture☆18May 8, 2025Updated last year
- Train and deploy LUT-based neural networks on FPGAs☆118Jun 12, 2024Updated 2 years ago
- ☆30Apr 26, 2019Updated 7 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- An MLIR-based toolchain for AMD AI Engine-enabled devices.☆667Updated this week
- TQT's pytorch implementation.☆22Dec 17, 2021Updated 4 years ago
- Generates intermediate tensor outputs for tflite☆15Apr 12, 2019Updated 7 years ago
- [TCAD 2021] Block Convolution: Towards Memory-Efficient Inference of Large-Scale CNNs on FPGA☆17Jul 7, 2022Updated 4 years ago
- ☆142Updated this week
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆70Aug 1, 2025Updated 11 months ago
- ☆11Jan 25, 2023Updated 3 years ago
- Digital Signal Processing Compiler in MLIR☆30Jul 15, 2025Updated last year
- An alternative Vivado custom design example (to fully Vitis) for the User Logic Partition targeting VCK5000☆14Jul 16, 2024Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Mar 17, 2022Updated 4 years ago
- A tool to generate optimized hardware files for univariate functions.☆30Apr 5, 2024Updated 2 years ago
- Code to accompany "Weightless Neural Networks for Efficient Edge Inference", PACT 2022☆22Nov 15, 2022Updated 3 years ago
- [DATE 2025] Official implementation and dataset of AIrchitect v2: Learning the Hardware Accelerator Design Space through Unified Represen…☆20Jan 17, 2025Updated last year
- Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-level Sparsity via Mixture-of-Experts☆140May 10, 2024Updated 2 years ago
- Adaptive floating-point based numerical format for resilient deep learning☆14Apr 11, 2022Updated 4 years ago
- ☆32Mar 31, 2025Updated last year
- Polyhedral High-Level Synthesis in MLIR☆35Mar 17, 2023Updated 3 years ago
- ☆18Feb 13, 2021Updated 5 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- The project is a simple example about how to use TensorFlow to train a ConNet model from labeled dataset and then use Vitis AI tools to d…☆16Aug 15, 2020Updated 5 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆99Oct 2, 2021Updated 4 years ago
- DeiT implementation for Q-ViT☆26Apr 21, 2025Updated last year
- This is a personal archive. Please refer to github.com/UCLA-VAST/RapidStream☆15May 31, 2022Updated 4 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆77Dec 19, 2025Updated 7 months ago
- [HPCA 2023] ViTCoD: Vision Transformer Acceleration via Dedicated Algorithm and Accelerator Co-Design☆133Jun 27, 2023Updated 3 years ago
- This repository contains the hardware implementation for Static BFP convolution on FPGA☆10Oct 15, 2019Updated 6 years ago