Alternatives and similar repositories for MaxEVA

Users that are interested in MaxEVA are comparing it to the libraries listed below

• UCLA-VAST / FlexCNN
  ☆71Updated 2 years ago
• horizon-research / systolic-array-dataflow-optimizer
  A general framework for optimizing DNN dataflow on systolic array
  ☆39Updated 4 years ago
• jha-lab / codebench
  [TECS'23] A project on the co-design of Accelerators and CNNs.
  ☆20Updated 2 years ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆80Updated 11 months ago
• sfu-arch / SpGEMM
  ☆36Updated 4 years ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆37Updated 5 years ago
• synergy-noc-generators / Proteus
  ☆10Updated 2 years ago
• DNN-Accelerators / Open-Source-IPs
  ☆33Updated 6 years ago
• gicLAB / SECDA
  ☆24Updated 2 years ago
• Sibylau / HLS_designs
  Systolic array implementations for Cholesky, LU, and QR decomposition
  ☆42Updated 8 months ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆79Updated 3 years ago
• fffasttime / AnyPackingNet
  ☆27Updated 3 months ago
• pku-liang / TensorLib
  A Spatial Accelerator Generation Framework for Tensor Algebra.
  ☆58Updated 3 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆45Updated 3 years ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆93Updated 9 months ago
• template-hls / template-hls-float
  ☆29Updated 6 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• sharc-lab / FPGA_ECE8893
  ☆35Updated 3 months ago
• arc-research-lab / AIM
  AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…
  ☆24Updated last month
• awai54st / Logic-Shrinkage
  ☆23Updated 2 years ago
• harvard-acc / ESP_Systolic_Array_Accelerator
  ☆4Updated 4 years ago
• Accelergy-Project / accelergy-timeloop-infrastructure
  Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop
  ☆54Updated 3 months ago
• MartaAndronic / NeuraLUT
  NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions
  ☆37Updated 3 months ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆46Updated 4 months ago
• GATECH-EIC / DNN-Chip-Predictor
  [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…
  ☆25Updated 2 years ago
• CASR-HKU / DPACS
  ☆18Updated 2 years ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆54Updated last week
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆65Updated 3 years ago
• ebby-s / MX-for-FPGA
  Implementation of Microscaling data formats in SystemVerilog.
  ☆21Updated last week
• GATECH-EIC / AutoDNNchip
  ☆71Updated 5 years ago