enyac-group / MaxEVALinks
MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)
☆20Updated last year
Alternatives and similar repositories for MaxEVA
Users that are interested in MaxEVA are comparing it to the libraries listed below
Sorting:
- NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions☆32Updated 2 months ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- ☆33Updated 6 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 3 months ago
- ☆29Updated 6 years ago
- ☆71Updated 2 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- ☆8Updated 2 years ago
- ☆35Updated 4 years ago
- ☆23Updated 2 years ago
- Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…☆19Updated 5 years ago
- ☆35Updated 2 months ago
- A DAG processor and compiler for a tree-based spatial datapath.☆13Updated 2 years ago
- ☆27Updated 2 months ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- Implementation of Microscaling data formats in SystemVerilog.☆19Updated 9 months ago
- ☆24Updated 4 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆57Updated 3 years ago
- A general framework for optimizing DNN dataflow on systolic array☆36Updated 4 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆52Updated last month
- ☆10Updated 2 years ago
- ☆4Updated 4 years ago
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆36Updated 2 weeks ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Updated 2 years ago
- ☆58Updated 5 years ago
- ☆26Updated last year
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 3 years ago
- Generate versal system design from ONNX model. AI engine kernels. Sub-microsecond speeds for autoencoders.☆14Updated 5 months ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆91Updated 8 months ago