enyac-group / MaxEVA
MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)
☆15Updated 7 months ago
Related projects ⓘ
Alternatives and complementary repositories for MaxEVA
- ☆24Updated 8 months ago
- ☆33Updated 3 years ago
- ☆70Updated last year
- ☆20Updated 2 years ago
- ☆27Updated 5 years ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆26Updated 4 months ago
- Designs for finalist teams of the DAC System Design Contest☆35Updated 4 years ago
- ☆32Updated 5 years ago
- ☆18Updated last year
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆19Updated this week
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- ☆3Updated 3 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 3 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆65Updated 3 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆71Updated 3 months ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆44Updated 2 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆46Updated 2 weeks ago
- An LSTM template and a few examples using Vivado HLS☆42Updated 6 months ago
- ☆18Updated last year
- HLS implemented systolic array structure☆41Updated 7 years ago
- CNN Accelerator in Frequency Domain☆10Updated 4 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆52Updated 2 years ago
- CNN accelerator☆27Updated 7 years ago
- Open-source of MSD framework☆14Updated last year
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆42Updated 2 years ago
- Serpens is an HBM FPGA accelerator for SpMV☆16Updated 3 months ago
- ☆25Updated 7 months ago
- An HLS based winograd systolic CNN accelerator☆48Updated 3 years ago
- PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…☆44Updated 9 months ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆38Updated 6 months ago