MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)
☆22Apr 17, 2024Updated 2 years ago
Alternatives and similar repositories for MaxEVA
Users that are interested in MaxEVA are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A compiler for lowering quantized ML models to AMD AI Engine (AIE) firmware.☆21Updated this week
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆176Mar 12, 2026Updated 5 months ago
- Generate versal system design from ONNX model. AI engine kernels. Sub-microsecond speeds for autoencoders.☆20Dec 29, 2024Updated last year
- Hands-on experience programming AI Engines using Vitis Unified Software Platform☆42Jul 24, 2024Updated 2 years ago
- Xilinx Modifications to Halide☆13May 3, 2021Updated 5 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- ☆25Jun 14, 2026Updated 2 months ago
- ☆11Sep 3, 2022Updated 3 years ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆38Mar 12, 2026Updated 5 months ago
- An MLIR-based compiler from C/C++ to AMD-Xilinx Versal AIE☆17Aug 5, 2022Updated 4 years ago
- Python functions and scripts to analyse cyclostationary signals☆26Feb 14, 2023Updated 3 years ago
- Reconfigurable Stream Network Architecture☆18Aug 13, 2026Updated 2 weeks ago
- Train and deploy LUT-based neural networks on FPGAs☆121Jun 12, 2024Updated 2 years ago
- ☆30Apr 26, 2019Updated 7 years ago
- A close-to-metal Python API for programming AMD Ryzen™ AI NPUs (AI Engines), built on an open-source MLIR-based compiler toolchain.☆685Updated this week
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- TQT's pytorch implementation.☆22Dec 17, 2021Updated 4 years ago
- Generates intermediate tensor outputs for tflite☆15Apr 12, 2019Updated 7 years ago
- [TCAD 2021] Block Convolution: Towards Memory-Efficient Inference of Large-Scale CNNs on FPGA☆17Jul 7, 2022Updated 4 years ago
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆74Aug 1, 2025Updated last year
- Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware☆49Jul 24, 2024Updated 2 years ago
- McPAT modeling framework☆13Oct 18, 2014Updated 11 years ago
- Digital Signal Processing Compiler in MLIR☆32Jul 15, 2025Updated last year
- An alternative Vivado custom design example (to fully Vitis) for the User Logic Partition targeting VCK5000☆14Jul 16, 2024Updated 2 years ago
- [ICML 2021] "Auto-NBA: Efficient and Effective Search Over the Joint Space of Networks, Bitwidths, and Accelerators" by Yonggan Fu, Yonga…☆16Jan 3, 2022Updated 4 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Mar 17, 2022Updated 4 years ago
- A tool to generate optimized hardware files for univariate functions.☆30Apr 5, 2024Updated 2 years ago
- Code to accompany "Weightless Neural Networks for Efficient Edge Inference", PACT 2022☆22Nov 15, 2022Updated 3 years ago
- [DATE 2025] Official implementation and dataset of AIrchitect v2: Learning the Hardware Accelerator Design Space through Unified Represen…☆21Jan 17, 2025Updated last year
- Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-level Sparsity via Mixture-of-Experts☆143May 10, 2024Updated 2 years ago
- The VD100 development board is based on the Xilinx Versal AI Edge series chip xcve2302 and is designed with a core board and a bottom boa…☆20Jul 9, 2024Updated 2 years ago
- Adaptive floating-point based numerical format for resilient deep learning☆14Apr 11, 2022Updated 4 years ago
- ☆32Mar 31, 2025Updated last year
- Polyhedral High-Level Synthesis in MLIR☆35Mar 17, 2023Updated 3 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆99Oct 2, 2021Updated 4 years ago
- DeiT implementation for Q-ViT☆26Apr 21, 2025Updated last year
- This is a personal archive. Please refer to github.com/UCLA-VAST/RapidStream☆15May 31, 2022Updated 4 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆77Dec 19, 2025Updated 8 months ago
- HLS Custom-Precision Floating-Point Library☆13Nov 6, 2017Updated 8 years ago
- [HPCA 2023] ViTCoD: Vision Transformer Acceleration via Dedicated Algorithm and Accelerator Co-Design☆134Jun 27, 2023Updated 3 years ago
- This repository contains the hardware implementation for Static BFP convolution on FPGA☆10Oct 15, 2019Updated 6 years ago