da-steve101 / radio_modulation

Related projects ⓘ

Alternatives and complementary repositories for radio_modulation

• JennySmith888 / 100GBE-PYNQ
  ☆18Updated 3 years ago
• da-steve101 / twn_generator
  Generate an FPGA design for a TWN
  ☆9Updated 5 years ago
• Xilinx / RFSoC2x2-PYNQ
  RFSoC2x2 board repo for PYNQ
  ☆17Updated 2 years ago
• strath-sdr / rfsoc_notebooks
  A collection of RFSoC introductory notebooks for PYNQ.
  ☆19Updated 3 years ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆24Updated 4 years ago
• Xilinx / DSP-PYNQ
  A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+
  ☆37Updated 2 years ago
• strath-sdr / pynq_agc
  Demonstration of Automatic Gain Control with PYNQ
  ☆11Updated 2 years ago
• sarafs1926 / ZCU216-PYNQ
  Board repo for the ZCU216 RFSOC
  ☆25Updated 2 years ago
• MicrochipTech / fpga-hls-examples
  Open-Source HLS Examples for Microchip FPGAs
  ☆38Updated 2 weeks ago
• strath-sdr / rfsoc_frequency_planner
  An RFSoC Frequency Planner developed using Python.
  ☆20Updated last year
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆67Updated 5 months ago
• Xilinx / brevitas-radioml-challenge-21
  ☆15Updated 3 years ago
• strath-sdr / rfsoc_qpsk
  PYNQ example of using the RFSoC as a QPSK transceiver.
  ☆91Updated last year
• MakarenaLabs / Xilinx-FPGA-HLS-PYNQ-ALVEO-Flow
  Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.
  ☆25Updated 4 years ago
• Xilinx / RFNoC-HLS-NeuralNet
  ☆104Updated 5 years ago
• Xilinx / RFSoC-PYNQ
  Python productivity for RFSoC platforms
  ☆57Updated 6 months ago
• strath-sdr / rfsoc_studio
  The Strathclyde RFSoC Studio Installer for PYNQ.
  ☆26Updated last year
• KastnerRG / Read_the_docs
  Projects and Labs for the Parallel Programming for FPGAs book
  ☆14Updated last week
• liuguangxi / gng
  Gaussian noise generator Verilog IP core
  ☆28Updated last year
• FPGA4HEP / course_material
  ☆35Updated 5 years ago
• Lcrypto / FEC-Archive-Verilog
  Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…
  ☆54Updated last year
• Xilinx / SDFEC-PYNQ
  A PYNQ overlay demonstrating the Xilinx RFSoC SD-FEC
  ☆13Updated 2 years ago
• AlexMontgomerie / fpgaconvnet-model
  Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.
  ☆27Updated 2 weeks ago
• MartaAndronic / PolyLUT
  PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…
  ☆44Updated 9 months ago
• Xilinx / Vitis_Model_Composer
  Vitis Model Composer Examples and Tutorials
  ☆75Updated this week
• srohit0 / CORDIC
  CORDIC VLSI-IP for deep learning activation functions
  ☆13Updated 5 years ago
• hukenovs / fp23fftk
  Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).
  ☆55Updated 2 years ago
• xupgit / compute_acceleration
  ☆12Updated 4 years ago
• Xilinx / PYNQ_RFSOC_Workshop
  Open-sourcing the PYNQ & RFSoC workshop materials
  ☆56Updated 4 years ago