Alternatives and similar repositories for radio_modulation

Users that are interested in radio_modulation are comparing it to the libraries listed below

• JennySmith888 / 100GBE-PYNQ
  ☆19Updated 3 years ago
• da-steve101 / twn_generator
  Generate an FPGA design for a TWN
  ☆10Updated 5 years ago
• strath-sdr / rfsoc_notebooks
  A collection of RFSoC introductory notebooks for PYNQ.
  ☆23Updated 3 years ago
• V0XNIHILI / parametrizable-floating-point-verilog
  Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent
  ☆28Updated 5 months ago
• Xilinx / RFNoC-HLS-NeuralNet
  ☆108Updated 6 years ago
• Xilinx / DSP-PYNQ
  A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+
  ☆39Updated 3 years ago
• hlslibs / ac_math
  Algorithmic C Math Library
  ☆65Updated 2 months ago
• Xilinx / RFSoC2x2-PYNQ
  RFSoC2x2 board repo for PYNQ
  ☆17Updated 2 years ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 5 years ago
• liuguangxi / gng
  Gaussian noise generator Verilog IP core
  ☆31Updated 2 years ago
• kkiningh / cs231n-project
  CNN accelerator
  ☆27Updated 8 years ago
• lite-david / comet
  RISC-V ISA based 32-bit processor written in HLS
  ☆16Updated 5 years ago
• Xilinx / brevitas-radioml-challenge-21
  ☆16Updated 3 years ago
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆51Updated 2 years ago
• Xilinx / logicnets
  Train and deploy LUT-based neural networks on FPGAs
  ☆97Updated last year
• Lcrypto / FEC-Archive-Verilog
  Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…
  ☆76Updated 2 years ago
• Xilinx / gemx
  Matrix Operation Library for FPGA https://xilinx.github.io/gemx/
  ☆63Updated 5 years ago
• strath-sdr / rfsoc_studio
  The Strathclyde RFSoC Studio Installer for PYNQ.
  ☆32Updated 2 years ago
• cornell-brg / pymtl-tut-hls
  Tutorial for integrating PyMTL and Vivado HLS
  ☆19Updated 9 years ago
• strath-sdr / rfsoc_ofdm
  PYNQ example of an OFDM Transmitter and Receiver on RFSoC.
  ☆50Updated 2 years ago
• fpgasystems / ZipML-PYNQ
  Linear model training using stochastic gradient descent (SGD) on PYNQ with full to low precision.
  ☆55Updated 7 years ago
• strath-sdr / pynq_agc
  Demonstration of Automatic Gain Control with PYNQ
  ☆15Updated 3 years ago
• Mshivam2409 / LDPC-Decoder
  Implementation of Partially Parellel LDPC Code Decoder in Verilog
  ☆14Updated 5 years ago
• MicrochipTech / fpga-hls-examples
  Open-Source HLS Examples for Microchip FPGAs
  ☆45Updated last month
• DreamIP / haddoc2
  Caffe to VHDL
  ☆67Updated 5 years ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆35Updated 7 years ago
• hlslibs / hls_tutorials
  Tutorials on HLS Design
  ☆52Updated 5 years ago
• strath-sdr / rfsoc_frequency_planner
  An RFSoC Frequency Planner developed using Python.
  ☆29Updated 2 years ago
• scale-lab / DRUM
  The Verilog source code for DRUM approximate multiplier.
  ☆31Updated 2 years ago
• strath-sdr / rfsoc_qpsk
  PYNQ example of using the RFSoC as a QPSK transceiver.
  ☆105Updated 2 years ago