Updated version of the XUP Workshops
☆18Aug 10, 2018Updated 7 years ago
Alternatives and similar repositories for Embedded-System-Design-Flow-on-Zynq
Users that are interested in Embedded-System-Design-Flow-on-Zynq are comparing it to the libraries listed below
Sorting:
- "mmult" example using SDSoC for PYNQ board☆11Feb 23, 2017Updated 9 years ago
- Chinese Guide for Alveo Getting Started☆12May 18, 2020Updated 5 years ago
- Updated Xilinx PYNQ for Zynq + ZynqMP python HW acceleration development☆12Mar 16, 2018Updated 7 years ago
- ☆30Mar 19, 2019Updated 6 years ago
- Open source/hardware SoC plattform based on the lattice mico 32 softcore☆15Apr 10, 2010Updated 15 years ago
- Scripts to automate the process of building an image for the Xilinx PYNQ project. This repository is deprecated as its functionality is n…☆20Feb 21, 2017Updated 9 years ago
- Verilog language support in Atom☆18Jun 30, 2019Updated 6 years ago
- ☆18Jul 19, 2018Updated 7 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆107May 5, 2018Updated 7 years ago
- CPOL=0, CPHA=0 SPI core for practicing formal verification with yosys☆21May 20, 2020Updated 5 years ago
- Simple AMP Running Linux and Bare-Metal System on Both Zynq SoC Processors☆22Dec 17, 2015Updated 10 years ago
- ☆24Dec 3, 2021Updated 4 years ago
- vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.☆26Jan 7, 2016Updated 10 years ago
- Obsolete repository of official HUAWEI CLOUD FPGA Development Kit //github.com/huaweicloud/huaweicloud-fpga☆26Oct 8, 2018Updated 7 years ago
- PYNQ, Neural network Language model, Overlay☆112Apr 26, 2019Updated 6 years ago
- Simple AlexNet forward path implementation in Matlab☆25Nov 8, 2021Updated 4 years ago
- Repository used to support automated builds under PetaLinux tools that use Yocto.☆63Mar 27, 2025Updated 11 months ago
- ☆30Apr 26, 2019Updated 6 years ago
- Provides Spatial with front-end support from popular machine learning frameworks☆34Sep 30, 2019Updated 6 years ago
- ☆30Mar 21, 2018Updated 7 years ago
- Embedded Microprocessor System Design using FPGAs 1. edition ISBN:☆12Apr 1, 2025Updated 11 months ago
- Language for simplifying parameterized RTL design☆12Nov 6, 2024Updated last year
- FIR band-pass filter using Verilog HDL.☆12Sep 6, 2020Updated 5 years ago
- Pynq projects and guides☆29Sep 11, 2018Updated 7 years ago
- Robotics Learning Note☆11Jun 22, 2018Updated 7 years ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆37Jul 10, 2019Updated 6 years ago
- This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.☆87Jun 29, 2023Updated 2 years ago
- A Comprehensive Model-Based Analysis Framework for High Level Synthesis of Real Applications☆38Oct 20, 2020Updated 5 years ago
- Change part number or package in a Xilinx 7-series FPGA bitstream☆44Apr 27, 2020Updated 5 years ago
- The project is intended to demonstrate Lane tracking & detection on Qualcomm’s Robotics Platform RB5. YOLOP is the architecture used to i…☆10Aug 22, 2023Updated 2 years ago
- A C# program that takes pictures at different focus distances and reconstructs a 3D model from the stack☆29Nov 22, 2013Updated 12 years ago
- ML.NET playground☆13Jun 14, 2019Updated 6 years ago
- ROS driver for iXblue inertial sensors supporting StdBin protocol☆10Feb 5, 2024Updated 2 years ago
- Repositorio utilizado para el Curso de Hadoop en Platzi☆11Dec 9, 2020Updated 5 years ago
- Python program that downloads past Powerball and Mega Millions winning numbers in an easy to read excel format. This project uses the Ope…☆13Aug 23, 2020Updated 5 years ago
- This repository manages DSD lab code files.☆14Oct 29, 2021Updated 4 years ago
- This repository provides a method to dynamically change the clock output frequency, phase shift, and duty cycle of the mixed-mode clock m…☆14Nov 4, 2020Updated 5 years ago
- A design of 15-order FIR filter using Verilog, with modulation and demodulation system using MATLAB☆10Aug 15, 2020Updated 5 years ago
- PYNQ-Z1 board files for Vivado☆35Jan 8, 2022Updated 4 years ago