Updated version of the XUP Workshops
☆19Aug 10, 2018Updated 8 years ago
Alternatives and similar repositories for Embedded-System-Design-Flow-on-Zynq
Users that are interested in Embedded-System-Design-Flow-on-Zynq are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Chinese Guide for Alveo Getting Started☆13May 18, 2020Updated 6 years ago
- "mmult" example using SDSoC for PYNQ board☆12Feb 23, 2017Updated 9 years ago
- Updated Xilinx PYNQ for Zynq + ZynqMP python HW acceleration development☆13Mar 16, 2018Updated 8 years ago
- ☆25Dec 3, 2021Updated 4 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆107May 5, 2018Updated 8 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- PYNQ demo as seen at FPL 2018☆22Nov 23, 2020Updated 5 years ago
- Obsolete repository of official HUAWEI CLOUD FPGA Development Kit //github.com/huaweicloud/huaweicloud-fpga☆26Oct 8, 2018Updated 8 years ago
- ☆30Mar 21, 2018Updated 8 years ago
- Scripts to automate the process of building an image for the Xilinx PYNQ project. This repository is deprecated as its functionality is n…☆20Feb 21, 2017Updated 9 years ago
- 2021 Xilinx China Winter Camp☆11Mar 12, 2021Updated 5 years ago
- Simple AMP Running Linux and Bare-Metal System on Both Zynq SoC Processors☆23Dec 17, 2015Updated 10 years ago
- ☆30Apr 26, 2019Updated 7 years ago
- PYNQ, Neural network Language model, Overlay☆112Apr 26, 2019Updated 7 years ago
- A sample Qt HMI sdk to use with sdl_core, which encapsulated json parser☆10Jan 2, 2019Updated 7 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- FPGA synthesis tool powered by equality saturation and program synthesis.☆15Jan 9, 2026Updated 9 months ago
- Integration Guidelines for SDL Core into the vehicle HMI☆12Oct 26, 2022Updated 3 years ago
- Pynq projects and guides☆29Sep 11, 2018Updated 8 years ago
- Open source/hardware SoC plattform based on the lattice mico 32 softcore☆15Apr 10, 2010Updated 16 years ago
- ILAng documentation☆12Nov 2, 2025Updated 11 months ago
- Synthesizable Higher-Order Functions (Patterns) for C++☆18Oct 3, 2018Updated 8 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆34Sep 19, 2018Updated 8 years ago
- ☆12Jun 4, 2018Updated 8 years ago
- Simple AlexNet forward path implementation in Matlab☆26Nov 8, 2021Updated 4 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Implementation of SIMPLE CFD algorythm. University of Toronto☆11Jan 17, 2019Updated 7 years ago
- vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.☆25Jan 7, 2016Updated 10 years ago
- Stencil with Optimized Dataflow Architecture Compiler☆17May 4, 2020Updated 6 years ago
- 以嵌入式stm32单片机为控制芯片,用SIM800c实现联网通信,以阿里云服务器为通信中介及数据中心,以PHP网页为通信媒介,Android软件为用户交互工具的物联网共享单车锁☆12Feb 13, 2019Updated 7 years ago
- ☆13Jan 20, 2023Updated 3 years ago
- ☆11Dec 8, 2018Updated 7 years ago
- FYP on using e-graphs to solve smt bitvector problems☆16Jun 24, 2025Updated last year
- Repository used to support automated builds under PetaLinux tools that use Yocto.☆63Mar 27, 2025Updated last year
- Huffman encoding core (Vivado HLS Project)☆12Oct 15, 2019Updated 7 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- A Comprehensive Model-Based Analysis Framework for High Level Synthesis of Real Applications☆38Oct 20, 2020Updated 5 years ago
- ☆18Mar 7, 2019Updated 7 years ago
- CPOL=0, CPHA=0 SPI core for practicing formal verification with yosys☆21May 20, 2020Updated 6 years ago
- 基于HLS的高效深度卷积神经网络FPGA实现方法☆74Jun 11, 2019Updated 7 years ago
- Verilog language support in Atom☆18Jun 30, 2019Updated 7 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆62Nov 23, 2021Updated 4 years ago
- Fork of Hipacc generating code for Vivado HLS and Altera OpenCL☆24Oct 8, 2018Updated 8 years ago