wady101 / Embedded-System-Design-Flow-on-Zynq
Updated version of the XUP Workshops
☆18Updated 6 years ago
Alternatives and similar repositories for Embedded-System-Design-Flow-on-Zynq:
Users that are interested in Embedded-System-Design-Flow-on-Zynq are comparing it to the libraries listed below
- ☆26Updated 6 years ago
- This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.☆21Updated 6 years ago
- This project describes how the cv2PYNQ python library was built☆20Updated 6 years ago
- Convolution Neural Network of vgg19 model in verilog☆45Updated 7 years ago
- Design contest for DAC 2018☆17Updated 6 years ago
- This project is trying to create a base vitis platform to run with DPU☆47Updated 4 years ago
- The Verilog source code for DRUM approximate multiplier.☆29Updated last year
- An Synthesizable Deep Learning Library based on Xilinx High Level Synthesis(HLS) tool☆15Updated 7 years ago
- CNN accelerator☆27Updated 7 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆103Updated 6 years ago
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆100Updated 4 years ago
- Verilog Convolutional Neural Network on PYNQ☆28Updated 6 years ago
- A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…☆17Updated 6 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆45Updated 4 years ago
- PYNQ Composabe Overlays☆69Updated 7 months ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆41Updated 4 years ago
- RISC-V ISA based 32-bit processor written in HLS☆17Updated 5 years ago
- FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ☆19Updated 5 years ago
- Fast and Flexible FPGA development using Hierarchical Partial Reconfiguration (FPT 2022)☆12Updated 9 months ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆25Updated 5 years ago
- CNN Accelerator in Frequency Domain☆12Updated 4 years ago
- ☆43Updated 6 years ago
- ☆29Updated 6 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆23Updated 4 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆51Updated 6 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆50Updated 7 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆60Updated 8 years ago