wady101 / Embedded-System-Design-Flow-on-Zynq
Updated version of the XUP Workshops
☆18Updated 6 years ago
Alternatives and similar repositories for Embedded-System-Design-Flow-on-Zynq:
Users that are interested in Embedded-System-Design-Flow-on-Zynq are comparing it to the libraries listed below
- ☆28Updated 7 years ago
- Design contest for DAC 2018☆17Updated 7 years ago
- Convolution Neural Network of vgg19 model in verilog☆46Updated 7 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆62Updated 8 years ago
- The Verilog source code for DRUM approximate multiplier.☆30Updated 2 years ago
- Adding PR to the PYNQ Overlay☆17Updated 8 years ago
- ☆83Updated 4 years ago
- This project is trying to create a base vitis platform to run with DPU☆47Updated 4 years ago
- PYNQ Composabe Overlays☆71Updated 10 months ago
- ☆65Updated 2 years ago
- ☆64Updated 6 years ago
- CNN accelerator☆28Updated 7 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆28Updated 2 years ago
- Hot & Spicy tool suite☆23Updated 3 years ago
- PYNQ demo as seen at FPL 2018☆21Updated 4 years ago
- Networking Overlay on PYNQ☆48Updated 6 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆51Updated 6 years ago
- Deploy CNN accelerator in embedded OS using SDSOC and Xilinx Ultrascale+ ZCU102 platform.☆25Updated 6 years ago
- 2019 SEU-Xilinx Summer School☆49Updated 5 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆50Updated 7 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆25Updated 4 years ago
- This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.☆21Updated 7 years ago
- A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…☆18Updated 7 years ago
- Fast and Flexible FPGA development using Hierarchical Partial Reconfiguration (FPT 2022)☆14Updated last year
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 4 years ago
- ☆14Updated 9 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆104Updated 7 years ago
- This project describes how the cv2PYNQ python library was built☆21Updated 6 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆112Updated 7 years ago
- Caffe to VHDL☆67Updated 4 years ago