wady101 / Embedded-System-Design-Flow-on-ZynqLinks
Updated version of the XUP Workshops
☆18Updated 6 years ago
Alternatives and similar repositories for Embedded-System-Design-Flow-on-Zynq
Users that are interested in Embedded-System-Design-Flow-on-Zynq are comparing it to the libraries listed below
Sorting:
- This project is trying to create a base vitis platform to run with DPU☆47Updated 4 years ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- Fast and Flexible FPGA development using Hierarchical Partial Reconfiguration (FPT 2022)☆14Updated last year
- Premade bitstreams and block designs to complemented the PYNQ overlay tutorial☆40Updated 3 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆105Updated 7 years ago
- PYNQ Composabe Overlays☆73Updated last year
- ☆29Updated 7 years ago
- ☆14Updated 9 years ago
- Convolution Neural Network of vgg19 model in verilog☆47Updated 7 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 5 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- Adding PR to the PYNQ Overlay☆17Updated 8 years ago
- Generic FIFO implementation with optional FWFT☆58Updated 5 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆64Updated 8 years ago
- Pynq projects and guides☆28Updated 6 years ago
- An Synthesizable Deep Learning Library based on Xilinx High Level Synthesis(HLS) tool☆15Updated 8 years ago
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆10Updated last year
- CNN accelerator☆27Updated 8 years ago
- This project describes how the cv2PYNQ python library was built☆21Updated 6 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.☆21Updated 7 years ago
- PYNQ, Neural network Language model, Overlay☆107Updated 6 years ago
- Python package which accelerates OpenCV image filtering functions for the PYNQ framework☆48Updated 6 years ago
- A Convolutional Neural Network (CNN) hardware accelerator for image recognition☆13Updated 5 years ago
- A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…☆18Updated 7 years ago
- verilog CNN generator for FPGA☆34Updated 4 years ago
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆110Updated 5 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆53Updated 6 years ago
- ☆84Updated 4 years ago
- ☆66Updated 3 years ago