drichmond / HOPSLinks
Synthesizable Higher-Order Functions (Patterns) for C++
☆17Updated 6 years ago
Alternatives and similar repositories for HOPS
Users that are interested in HOPS are comparing it to the libraries listed below
Sorting:
- A Vivado HLS Command Line Helper Tool☆36Updated 3 years ago
- Python implementations of fixed size hardware types (Bit, BitVector, UInt, SInt, ...) based on the SMT-LIB2 semantics☆18Updated last year
- A collection of big designs to run post-synthesis simulations with yosys☆50Updated 9 years ago
- FGPU is a soft GPU architecture general purpose computing☆60Updated 4 years ago
- hardware library for hwt (= ipcore repo)☆41Updated 3 weeks ago
- Debuggable hardware generator☆69Updated 2 years ago
- FPGA implementation of deflate (de)compress RFC 1950/1951☆62Updated 6 years ago
- This store contains Configurable Example Designs.☆48Updated this week
- A Python package for testing hardware (part of the magma ecosystem)☆43Updated last year
- Open Application-Specific Instruction Set processor tools (OpenASIP)☆162Updated 2 months ago
- Algorithmic C Datatypes☆129Updated 2 months ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆124Updated last year
- The Task Parallel System Composer (TaPaSCo)☆111Updated 2 months ago
- PACoGen: Posit Arithmetic Core Generator☆75Updated 5 years ago
- FPGA tool performance profiling☆102Updated last year
- Open-Source Posit RISC-V Core with Quire Capability☆62Updated 6 months ago
- Facilitates building open source tools for working with hardware description languages (HDLs)☆64Updated 5 years ago
- Chisel library for Unum Type-III Posit Arithmetic☆39Updated 4 months ago
- Next generation CGRA generator☆113Updated last week
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆83Updated 10 months ago
- A SystemVerilog source file pickler.☆59Updated 9 months ago
- Library of example SystemC/TLM peripherals for various SoCs based on the SCS library☆14Updated last month
- The Shang high-level synthesis framework☆120Updated 11 years ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆215Updated 3 weeks ago
- FPGA version of Rodinia in HLS C/C++☆38Updated 4 years ago
- Xilinx Unisim Library in Verilog☆82Updated 5 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- A framework for FPGA emulation of mixed-signal systems☆36Updated 4 years ago
- Tools for working with circuits as graphs in python☆122Updated last year
- A library and command-line tool for querying a Verilog netlist.☆27Updated 3 years ago