drichmond / HOPS
Synthesizable Higher-Order Functions (Patterns) for C++
☆17Updated 6 years ago
Alternatives and similar repositories for HOPS:
Users that are interested in HOPS are comparing it to the libraries listed below
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- A Vivado HLS Command Line Helper Tool☆36Updated 3 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆38Updated 7 months ago
- FPGA acceleration of arbitrary precision floating point computations.☆38Updated 2 years ago
- FGPU is a soft GPU architecture general purpose computing☆57Updated 4 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 8 months ago
- Algorithmic C Math Library☆61Updated 4 months ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆25Updated 4 years ago
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆44Updated 4 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆51Updated 5 years ago
- FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.☆54Updated 4 months ago
- This store contains Configurable Example Designs.☆44Updated this week
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆18Updated 2 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆47Updated 8 years ago
- Xilinx Unisim Library in Verilog☆76Updated 4 years ago
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Updated 5 years ago
- hardware library for hwt (= ipcore repo)☆37Updated 5 months ago
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- ☆55Updated 2 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆120Updated 10 months ago
- C++17 implementation of an AST for Verilog code generation☆24Updated last year
- FOS - FPGA Operating System☆66Updated 4 years ago
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago
- FPGA implementation of deflate (de)compress RFC 1950/1951☆60Updated 5 years ago
- Open-Source Posit RISC-V Core with Quire Capability☆56Updated 2 months ago
- ☆57Updated this week
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- Open-Source HLS Examples for Microchip FPGAs☆44Updated 3 weeks ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆16Updated 5 years ago