drichmond / HOPS
Synthesizable Higher-Order Functions (Patterns) for C++
☆16Updated 6 years ago
Related projects ⓘ
Alternatives and complementary repositories for HOPS
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆36Updated 2 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆49Updated 4 years ago
- A Vivado HLS Command Line Helper Tool☆36Updated 3 years ago
- FPGA acceleration of arbitrary precision floating point computations.☆38Updated 2 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 3 months ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 2 years ago
- Open-Source Posit RISC-V Core with Quire Capability☆45Updated this week
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆95Updated last year
- PACoGen: Posit Arithmetic Core Generator☆64Updated 5 years ago
- Open-Source HLS Examples for Microchip FPGAs☆38Updated 3 weeks ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆16Updated last year
- Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware☆46Updated 4 months ago
- A polyhedral compiler for hardware accelerators☆56Updated 4 months ago
- Xilinx Unisim Library in Verilog☆71Updated 4 years ago
- Introductory examples for using PYNQ with Alveo☆48Updated last year
- This store contains Configurable Example Designs.☆42Updated last week
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- ☆24Updated 2 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆59Updated 3 years ago
- HLS for Networks-on-Chip☆31Updated 3 years ago
- ☆52Updated 2 years ago
- FGPU is a soft GPU architecture general purpose computing☆56Updated 4 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆44Updated 8 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆24Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆39Updated 4 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆58Updated 2 months ago
- Chisel library for Unum Type-III Posit Arithmetic☆32Updated 7 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆36Updated last month
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Updated 5 years ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆14Updated 5 years ago