Alternatives and similar repositories for HOPS

Users that are interested in HOPS are comparing it to the libraries listed below

• benjmarshall / hlsclt
  A Vivado HLS Command Line Helper Tool
  ☆36Updated 3 years ago
• hlslibs / matchlib_connections
  Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)
  ☆38Updated 2 weeks ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆57Updated 7 months ago
• FPGA-Research / zynq-ultrascale-readback-capture
  This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…
  ☆16Updated 5 years ago
• malkadi / FGPU
  FGPU is a soft GPU architecture general purpose computing
  ☆57Updated 4 years ago
• chipsalliance / fpga-interchange-schema
  ☆56Updated 2 years ago
• hlslibs / ac_math
  Algorithmic C Math Library
  ☆62Updated 2 weeks ago
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆18Updated 3 years ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆49Updated 9 years ago
• Xilinx / XilinxCEDStore
  This store contains Configurable Example Designs.
  ☆46Updated 3 weeks ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆65Updated 3 months ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆29Updated 8 years ago
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆37Updated 2 weeks ago
• os-fpga / FOEDAG
  Framework Open EDA Gui
  ☆65Updated 5 months ago
• openformal / sva_basics
  This repository is compilation of basics of System Verilog Assertions in context of formal verification
  ☆21Updated 6 years ago
• RSPwFPGAs / opae-xilinx
  OPAE porting to Xilinx FPGA devices.
  ☆39Updated 4 years ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆57Updated this week
• maltanar / rosetta
  Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ
  ☆33Updated 6 years ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆78Updated 4 years ago
• Xilinx / gemx
  Matrix Operation Library for FPGA https://xilinx.github.io/gemx/
  ☆64Updated 5 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆61Updated 7 months ago
• FPGA-Research / fos
  FOS - FPGA Operating System
  ☆68Updated 4 years ago
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆42Updated this week
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆27Updated 2 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆33Updated this week
• thoughtworks / hardposit-chisel3
  Chisel library for Unum Type-III Posit Arithmetic
  ☆38Updated 2 months ago
• spcl / apfp
  FPGA acceleration of arbitrary precision floating point computations.
  ☆40Updated 3 years ago
• isi-rcg / spicy
  Hot & Spicy tool suite
  ☆23Updated 3 years ago
• CEatBTU / FGPU
  FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.
  ☆55Updated 5 months ago