Alternatives and similar repositories for models:

Users that are interested in models are comparing it to the libraries listed below

• DNN-Accelerators / Open-Source-IPs
  ☆33Updated 6 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆57Updated 3 years ago
• awai54st / LUTNet
  ☆57Updated 4 years ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆36Updated 4 years ago
• UCLA-VAST / FlexCNN
  ☆71Updated 2 years ago
• walkieq / RNN_HLS
  An LSTM template and a few examples using Vivado HLS
  ☆44Updated 10 months ago
• Xilinx / logicnets
  ☆87Updated 9 months ago
• AlexMontgomerie / samo
  SAMO: Streaming Architecture Mapping Optimisation
  ☆32Updated last year
• GATECH-EIC / AutoDNNchip
  ☆70Updated 5 years ago
• dimdano / adapt
  Fast Emulation of Approximate DNN Accelerators in PyTorch
  ☆22Updated last year
• Yang-YiFan / DiracDeltaNet
  PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs
  ☆31Updated 5 years ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆50Updated 3 years ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆70Updated 3 years ago
• cornell-zhang / FracBNN
  FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations
  ☆91Updated 3 years ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 4 years ago
• CASR-HKU / MSD-FCCM23
  Open-source of MSD framework
  ☆16Updated last year
• pulp-platform / stream-ebpc
  Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…
  ☆24Updated 4 years ago
• PSCLab-ASU / Systolic-CNN
  ☆15Updated 4 years ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆42Updated 3 weeks ago
• AlexMontgomerie / fpgaconvnet-tutorial
  A collection of tutorials for the fpgaConvNet framework.
  ☆41Updated 6 months ago
• ehw-fit / tf-approximate
  Approximate layers - TensorFlow extension
  ☆27Updated 11 months ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆77Updated 7 months ago
• mohaghasemzadeh / ReBNet
  Residual Binarized Neural Network
  ☆43Updated 6 years ago
• UCLA-VAST / CLINK
  Compact LSTM inference kernel (CLINK) designed in C/HLS for FPGA implementation.
  ☆17Updated 5 years ago
• KULeuven-MICAS / DeFiNES
  A framework for fast exploration of the depth-first scheduling space for DNN accelerators
  ☆37Updated 2 years ago
• awai54st / Logic-Shrinkage
  ☆23Updated 2 years ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆48Updated last month
• Accelergy-Project / processing-in-memory-design
  ☆26Updated 11 months ago
• MakarenaLabs / Xilinx-FPGA-HLS-PYNQ-ALVEO-Flow
  Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.
  ☆29Updated 4 years ago