fastmachinelearning / modelsLinks
Models and examples built with hls4ml
☆12Updated 5 years ago
Alternatives and similar repositories for models
Users that are interested in models are comparing it to the libraries listed below
Sorting:
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆57Updated 3 years ago
- ☆58Updated 5 years ago
- ☆33Updated 6 years ago
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆30Updated 5 years ago
- An LSTM template and a few examples using Vivado HLS☆45Updated last year
- ☆94Updated last year
- HLS implemented systolic array structure☆41Updated 7 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 4 years ago
- ☆71Updated 2 years ago
- Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.☆29Updated 7 months ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆52Updated 7 years ago
- Residual Binarized Neural Network☆43Updated 7 years ago
- ☆71Updated 5 years ago
- Compact LSTM inference kernel (CLINK) designed in C/HLS for FPGA implementation.☆17Updated 5 years ago
- SAMO: Streaming Architecture Mapping Optimisation☆33Updated last year
- NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions☆37Updated 2 months ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆94Updated 3 years ago
- MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)☆21Updated last year
- An HLS based winograd systolic CNN accelerator☆53Updated 3 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆51Updated 4 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆79Updated 11 months ago
- An OpenCL-Based FPGA Accelerator for Compressed YOLOv2☆37Updated 4 years ago
- ☆16Updated 4 years ago
- PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs☆31Updated 6 years ago
- FPGA and GPU acceleration of LeNet5☆34Updated 5 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆79Updated 3 years ago
- A collection of tutorials for the fpgaConvNet framework.☆41Updated 9 months ago
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago
- A high-level performance analysis tool for FPGA-based accelerators☆20Updated 8 years ago