V0XNIHILI / parametrizable-floating-point-verilogLinks
Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent
☆29Updated 7 months ago
Alternatives and similar repositories for parametrizable-floating-point-verilog
Users that are interested in parametrizable-floating-point-verilog are comparing it to the libraries listed below
Sorting:
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆15Updated 2 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆30Updated 4 months ago
- SRAM☆22Updated 5 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆43Updated 2 years ago
- An open source PDK using TIGFET 10nm devices.☆51Updated 2 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆72Updated 10 months ago
- SystemVerilog FSM generator☆32Updated last year
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- sram/rram/mram.. compiler☆42Updated 2 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆29Updated last year
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated 4 months ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Updated 3 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆31Updated 3 years ago
- ☆30Updated this week
- A tool to generate optimized hardware files for univariate functions.☆29Updated last year
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆27Updated 2 weeks ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆43Updated 2 years ago
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆17Updated 2 years ago
- matrix-coprocessor for RISC-V☆23Updated 6 months ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated this week
- A configurable SRAM generator☆56Updated 2 months ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆67Updated 8 months ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆41Updated this week
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆24Updated this week
- A Python package for generating HDL wrappers and top modules for HDL sources☆38Updated last week
- Library of open source Process Design Kits (PDKs)☆56Updated 2 weeks ago
- Open Source PHY v2☆31Updated last year