Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent
☆33Mar 13, 2025Updated last year
Alternatives and similar repositories for parametrizable-floating-point-verilog
Users that are interested in parametrizable-floating-point-verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Chameleon: A Multiplier-Free Temporal Convolutional Network Accelerator for End-to-End Few-Shot and Continual Learning from Sequential Da…☆30Oct 8, 2026Updated 3 weeks ago
- PACoGen: Posit Arithmetic Core Generator☆83Aug 16, 2019Updated 7 years ago
- ☆10Mar 11, 2017Updated 9 years ago
- Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…☆77Aug 10, 2024Updated 2 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Jul 8, 2013Updated 13 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components☆50May 20, 2021Updated 5 years ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆22May 12, 2025Updated last year
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆45May 5, 2023Updated 3 years ago
- Present Crypto Engine in Verilog☆13Feb 27, 2016Updated 10 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆84Jul 18, 2026Updated 3 months ago
- 32 bit pipelined binary floating point adder using IEEE-754 Single Precision Format in Verilog☆18Aug 27, 2020Updated 6 years ago
- ☆10Jan 22, 2026Updated 9 months ago
- Wrappers for open source FPU hardware implementations.☆37Nov 27, 2025Updated 11 months ago
- ☆15Nov 30, 2023Updated 2 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- This is the verilog implementation of IEEE 754 32 bit floating point multiplier☆12Jul 12, 2020Updated 6 years ago
- Create a working Rocket Chip bitstream for Xilinx boards on Ubuntu 24.04 LTS by Eugene Tarassov's GitHub repo☆11Apr 27, 2025Updated last year
- Implementing Different Adder Structures in Verilog☆78Sep 3, 2019Updated 7 years ago
- Revision Control Labs and Materials☆26Jan 23, 2018Updated 8 years ago
- Verilog based simulation modell for 7 Series PLL☆18May 4, 2020Updated 6 years ago
- LMS sound filtering by Verilog☆44Apr 5, 2020Updated 6 years ago
- Octave/MATLAB code for generating compensation FIR coefficients☆14Sep 7, 2015Updated 11 years ago
- safe, no-cost and easy-to-use Cpp header to work safely with HW registers☆14Sep 15, 2024Updated 2 years ago
- ☆12Nov 7, 2018Updated 7 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- C++ static vector class template. Also might be known as fixed vector or on-stack vector.☆13Jul 8, 2022Updated 4 years ago
- My own VHDL components library. Anything from a flip flop to an ALU.☆12Feb 5, 2024Updated 2 years ago
- VEXTPROJ - the version control friendly system for creation of Vivado projects☆13Oct 25, 2025Updated last year
- FIR band-pass filter using Verilog HDL.☆14Sep 7, 2026Updated last month
- A Deep Learning Framework for the Posit Number System☆31Aug 5, 2024Updated 2 years ago
- Ibex RISC-V core extended with hardware acceleration of cryptography functions☆14May 10, 2024Updated 2 years ago
- DRSAN repository☆10Aug 1, 2022Updated 4 years ago
- The 'missing header' for Chisel☆24Feb 5, 2026Updated 8 months ago
- ☆17Aug 26, 2025Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Artifacts for ATC '22 paper "Faster Software Packet Processing on FPGA NICs with eBPF Program Warping"☆18May 20, 2022Updated 4 years ago
- ☆14Feb 14, 2022Updated 4 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆15Feb 22, 2024Updated 2 years ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆15Apr 11, 2023Updated 3 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆103Apr 30, 2019Updated 7 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆45Apr 13, 2023Updated 3 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆125Apr 3, 2026Updated 6 months ago