V0XNIHILI / parametrizable-floating-point-verilog
Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent
☆24Updated 2 weeks ago
Alternatives and similar repositories for parametrizable-floating-point-verilog:
Users that are interested in parametrizable-floating-point-verilog are comparing it to the libraries listed below
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆14Updated last year
- SystemVerilog IPs and Modules for architectural redundancy designs.☆11Updated last month
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆38Updated 4 years ago
- APB UVC ported to Verilator☆11Updated last year
- Open FPGA Modules☆23Updated 5 months ago
- Pipelined FFT/IFFT 64 points processor☆12Updated 10 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆25Updated 4 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- Common SystemVerilog RTL modules for RgGen☆12Updated last month
- An open source PDK using TIGFET 10nm devices.☆48Updated 2 years ago
- Xilinx AXI VIP example of use☆34Updated 3 years ago
- SRAM☆21Updated 4 years ago
- sram/rram/mram.. compiler☆32Updated last year
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆18Updated 7 months ago
- APB Logic☆17Updated 3 months ago
- ☆25Updated this week
- Reconfigurable Binary Engine☆16Updated 4 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆17Updated 6 years ago
- The Verilog source code for DRUM approximate multiplier.☆29Updated last year
- CORDIC VLSI-IP for deep learning activation functions☆14Updated 5 years ago
- Library of open source Process Design Kits (PDKs)☆37Updated last week
- YosysHQ SVA AXI Properties☆37Updated 2 years ago
- A RRAM addon for the NCSU FreePDK 45nm☆23Updated 3 years ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆17Updated 2 years ago
- General Purpose AXI Direct Memory Access☆48Updated 10 months ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆18Updated 2 years ago
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆17Updated 2 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆26Updated 10 months ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆22Updated last week