Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent
☆33Mar 13, 2025Updated last year
Alternatives and similar repositories for parametrizable-floating-point-verilog
Users that are interested in parametrizable-floating-point-verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Chameleon: A Multiplier-Free Temporal Convolutional Network Accelerator for End-to-End Few-Shot and Continual Learning from Sequential Da…☆27Mar 5, 2026Updated 5 months ago
- Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…☆72Aug 10, 2024Updated 2 years ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆21May 12, 2025Updated last year
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Jul 8, 2013Updated 13 years ago
- Verilog based simulation modell for 7 Series PLL☆17May 4, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆45May 5, 2023Updated 3 years ago
- 32 bit pipelined binary floating point adder using IEEE-754 Single Precision Format in Verilog☆18Aug 27, 2020Updated 5 years ago
- ☆15Nov 30, 2023Updated 2 years ago
- Present Crypto Engine in Verilog☆12Feb 27, 2016Updated 10 years ago
- Wrappers for open source FPU hardware implementations.☆37Nov 27, 2025Updated 8 months ago
- Implementing Different Adder Structures in Verilog☆77Sep 3, 2019Updated 6 years ago
- Revision Control Labs and Materials☆26Jan 23, 2018Updated 8 years ago
- An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components☆48May 20, 2021Updated 5 years ago
- A Deep Learning Framework for the Posit Number System☆31Aug 5, 2024Updated 2 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- FIR band-pass filter using Verilog HDL.☆13Sep 6, 2020Updated 5 years ago
- LMS sound filtering by Verilog☆43Apr 5, 2020Updated 6 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆82Jul 18, 2026Updated 3 weeks ago
- C++ static vector class template. Also might be known as fixed vector or on-stack vector.☆13Jul 8, 2022Updated 4 years ago
- DRSAN repository☆10Aug 1, 2022Updated 4 years ago
- Starlight: A Kernel Optimizer for GPU Processing☆16Jan 10, 2024Updated 2 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆14Feb 22, 2024Updated 2 years ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆15Apr 11, 2023Updated 3 years ago
- VEXTPROJ - the version control friendly system for creation of Vivado projects☆13Oct 25, 2025Updated 9 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Formal Verification of RISC V IM Processor☆11Mar 27, 2022Updated 4 years ago
- Artifacts for ATC '22 paper "Faster Software Packet Processing on FPGA NICs with eBPF Program Warping"☆17May 20, 2022Updated 4 years ago
- ☆14Feb 14, 2022Updated 4 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆103Apr 30, 2019Updated 7 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆124Apr 3, 2026Updated 4 months ago
- ☆62Feb 18, 2019Updated 7 years ago
- A breakout board for FPGA Mezzanine Card (FMC) Low-pin count connectors.☆23Apr 24, 2019Updated 7 years ago
- A tiny FP8 multiplication unit written in Verilog. TinyTapeout 2 submission.☆14Nov 23, 2022Updated 3 years ago
- softfloat and softposit in Python☆15Aug 2, 2019Updated 7 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Documentation for the entire CGRAFlow☆19Sep 17, 2021Updated 4 years ago
- FIR Filter in Verilog☆15Nov 17, 2019Updated 6 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆630Jul 24, 2026Updated 2 weeks ago
- A chip8 emulator made in gameboy assembly for the gameboy☆16Aug 12, 2021Updated 4 years ago
- Ready-to-link, packaged Aurora IP on four QSFP28 lanes, providing 100Gb/s throughput, flow control and status monitoring☆18Jul 22, 2026Updated 2 weeks ago
- TMMA: A Tiled Matrix Multiplication Accelerator for Self-Attention Projections in Transformer Models, optimized for edge deployment on Xi…☆38Apr 7, 2026Updated 4 months ago
- MAC system with IEEE754 compatibility☆14Nov 22, 2023Updated 2 years ago