taneroksuz / fpu-spLinks
IEEE 754 single precision floating point library in systemverilog and vhdl
☆32Updated 9 months ago
Alternatives and similar repositories for fpu-sp
Users that are interested in fpu-sp are comparing it to the libraries listed below
Sorting:
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆29Updated 12 years ago
- ☆61Updated 4 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆51Updated 11 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆36Updated this week
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆21Updated 2 months ago
- Demo SoC for SiliconCompiler.☆61Updated this week
- A small 32-bit implementation of the RISC-V architecture☆32Updated 5 years ago
- 3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.☆90Updated 5 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆30Updated last year
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆95Updated this week
- RISC-V Nox core☆68Updated 2 months ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆50Updated last year
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆70Updated 9 months ago
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated 2 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- PicoRV☆44Updated 5 years ago
- This is a circular buffer controller used in FPGA.☆34Updated 9 years ago
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 8 months ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆67Updated this week
- Minimal DVI / HDMI Framebuffer☆82Updated 5 years ago
- Bitstream relocation and manipulation tool.☆47Updated 2 years ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 10 months ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆48Updated 4 months ago
- A simple DDR3 memory controller☆59Updated 2 years ago
- USB virtual model in C++ for Verilog☆31Updated 11 months ago
- A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board☆31Updated 4 years ago
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- M-extension for RISC-V cores.☆31Updated 10 months ago
- LunaPnR is a place and router for integrated circuits☆47Updated 2 months ago