taneroksuz / fpu-spView external linksLinks
IEEE 754 single precision floating point library in systemverilog and vhdl
☆40Jan 2, 2026Updated last month
Alternatives and similar repositories for fpu-sp
Users that are interested in fpu-sp are comparing it to the libraries listed below
Sorting:
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆81Jan 2, 2026Updated last month
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆20Nov 9, 2025Updated 3 months ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Aug 22, 2021Updated 4 years ago
- Generate symbols from HDL components/modules☆22Feb 6, 2023Updated 3 years ago
- ☆14Mar 21, 2022Updated 3 years ago
- A gdbstub for connecting GDB to a RISC-V Debug Module☆30Oct 7, 2024Updated last year
- Portable HyperRAM controller☆65Dec 8, 2024Updated last year
- Hardware/Software Co-design environment of a processor core for deterministic real time systems☆38Aug 19, 2023Updated 2 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆11May 6, 2019Updated 6 years ago
- ☆10Nov 8, 2019Updated 6 years ago
- Experiments with Cologne Chip's GateMate FPGA architecture☆17Nov 16, 2023Updated 2 years ago
- A small DNN library for RISC-V, using RISC-V Vector and Matrix extensions☆11Mar 13, 2025Updated 11 months ago
- RTL implementation of a ray-tracing GPU☆15Dec 18, 2012Updated 13 years ago
- A customized copy of OpenOCD able to access the jtagd/jtagserver distributed with Quartus. At present it is restricted to accessing the A…☆13Aug 18, 2025Updated 5 months ago
- ☆12May 29, 2020Updated 5 years ago
- Network protocol libraries for VHDL test benches☆13Jan 11, 2026Updated last month
- powerpc processor prototype and an example of semiconductor startup biz plan☆14Feb 2, 2019Updated 7 years ago
- correlate an SPI capture of an AMD boot procedure to the PSP firmware components☆15Jan 13, 2026Updated last month
- ADPCM decoder compatible with OKI 6295☆14Jan 6, 2025Updated last year
- RedPitaya application: Software Defined Radio (SDR) for an 8-channel WSPR receiver.☆10Jan 29, 2018Updated 8 years ago
- AES RoCC Accelerator☆10May 20, 2021Updated 4 years ago
- Original test vector of RISC-V Vector Extension☆14Mar 23, 2021Updated 4 years ago
- Approximate arithmetic circuits for FPGAs☆13Feb 19, 2020Updated 5 years ago
- Implementation of a RISC-V CPU in Verilog.☆17Mar 2, 2025Updated 11 months ago
- ☆30Jun 16, 2024Updated last year
- Automatically exported from code.google.com/p/playtag☆14Jan 9, 2023Updated 3 years ago
- 正点原子开拓者&新起点FPGA开发板例程☆15Nov 29, 2019Updated 6 years ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆125Jul 7, 2016Updated 9 years ago
- VHDL for basic floating-point operations.☆31Oct 2, 2018Updated 7 years ago
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆32Jan 30, 2025Updated last year
- A very simple RISC-V ISA emulator.☆39Dec 12, 2020Updated 5 years ago
- A tiny FP8 multiplication unit written in Verilog. TinyTapeout 2 submission.☆14Nov 23, 2022Updated 3 years ago
- 4 channel 1GS/s DDS (AD9910 or AD9912 variant)☆16Jul 7, 2025Updated 7 months ago
- A simple DSP library and command-line tool for Software Defined Radio.☆14Feb 2, 2026Updated 2 weeks ago
- ☆17Jan 21, 2026Updated 3 weeks ago
- ☆60Aug 30, 2021Updated 4 years ago
- A 2D mesh Network on Chip with 5-stage pipelined router, all implemented in Verilog and run on Artix-7 FPGA.☆16May 30, 2023Updated 2 years ago
- Baseband Receiver IP for GPS like DSSS signals☆40May 19, 2020Updated 5 years ago
- A computer (FPGA SoC) based on the MRISC32-A1 CPU☆55Sep 2, 2023Updated 2 years ago