taneroksuz / fpu-spLinks
IEEE 754 single precision floating point library in systemverilog and vhdl
☆32Updated 8 months ago
Alternatives and similar repositories for fpu-sp
Users that are interested in fpu-sp are comparing it to the libraries listed below
Sorting:
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆29Updated 12 years ago
- ☆61Updated 4 years ago
- Minimal DVI / HDMI Framebuffer☆83Updated 5 years ago
- Bitstream relocation and manipulation tool.☆47Updated 2 years ago
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆29Updated last year
- A small 32-bit implementation of the RISC-V architecture☆32Updated 5 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆24Updated 2 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆20Updated 2 months ago
- Demo SoC for SiliconCompiler.☆60Updated last week
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆48Updated last year
- Small SERV-based SoC primarily for OpenMPW tapeout☆47Updated 3 months ago
- Basic USB 1.1 Host Controller for small FPGAs☆93Updated 5 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆35Updated last week
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆94Updated this week
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆50Updated 10 months ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆106Updated last week
- FPGA based microcomputer sandbox for software and RTL experimentation☆66Updated last week
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 7 months ago
- This is a circular buffer controller used in FPGA.☆34Updated 9 years ago
- Wishbone interconnect utilities☆41Updated 7 months ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆29Updated 6 months ago
- Reusable Verilog 2005 components for FPGA designs☆46Updated 6 months ago
- ☆16Updated 5 years ago
- RISC-V Nox core☆68Updated last month
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- Mathematical Functions in Verilog☆94Updated 4 years ago