taneroksuz / fpu-spLinks
IEEE 754 single precision floating point library in systemverilog and vhdl
☆38Updated last year
Alternatives and similar repositories for fpu-sp
Users that are interested in fpu-sp are comparing it to the libraries listed below
Sorting:
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆30Updated 12 years ago
- Demo SoC for SiliconCompiler.☆62Updated last week
- Reusable Verilog 2005 components for FPGA designs☆49Updated last week
- Another tiny RISC-V implementation☆62Updated 4 years ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆74Updated this week
- ☆60Updated 4 years ago
- SoftCPU/SoC engine-V☆55Updated 9 months ago
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆22Updated last month
- Bitstream relocation and manipulation tool.☆50Updated 3 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆36Updated last year
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆109Updated last week
- Using VexRiscv without installing Scala☆39Updated 4 years ago
- Minimal DVI / HDMI Framebuffer☆83Updated 5 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆102Updated 3 weeks ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆50Updated 3 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 5 months ago
- PicoRV☆43Updated 5 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆31Updated 5 years ago
- Spen's Official OpenOCD Mirror☆51Updated 9 months ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆47Updated last week
- USB virtual model in C++ for Verilog☆32Updated last year
- 3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.☆91Updated 5 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆69Updated 7 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆51Updated last year
- RISC-V Nox core☆71Updated 5 months ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆81Updated 5 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆21Updated 4 years ago