Alternatives and similar repositories for lxp32-cpu

Users that are interested in lxp32-cpu are comparing it to the libraries listed below

• Wren6991 / Hazard5
  5-stage RISC-V CPU, originally developed for RISCBoy
  ☆31Updated 2 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated 4 months ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆69Updated 3 years ago
• smunaut / iCE40linux
  Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker
  ☆99Updated 2 years ago
• mrisc32 / mrisc32-a1
  A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA
  ☆24Updated last year
• gtjennings1 / HyperBUS
  A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs
  ☆60Updated 6 years ago
• m-labs / lm32
  LatticeMico32 soft processor
  ☆106Updated 10 years ago
• AntonMause / rv16poc
  16 bit RISC-V proof of concept
  ☆24Updated 10 months ago
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆81Updated 4 years ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆45Updated 5 months ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆38Updated 3 years ago
• olgirard / openmsp430
  The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
  ☆65Updated 7 years ago
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆52Updated 3 years ago
• OLIMEX / iCE40HX8K-EVB
  iCE40HX8K development board with SRAM and bus for fast ADC, DAC, IOs
  ☆38Updated 8 months ago
• nsauzede / cpu86
  🔌 CPU86 - Free VHDL CPU8088 IP core - ported to Papilio and Max1000 FPGA
  ☆45Updated 7 months ago
• mmicko / prjtang
  Documenting the Anlogic FPGA bit-stream format.
  ☆88Updated 2 years ago
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆91Updated 6 years ago
• lawrie / ulx3s_examples
  Example Verilog code for Ulx3s
  ☆40Updated 3 years ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆91Updated 5 years ago
• nand2mario / ddr3-tang-primer-20k
  DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.
  ☆56Updated 2 years ago
• cliffordwolf / PonyLink
  A single-wire bi-directional chip-to-chip interface for FPGAs
  ☆124Updated 9 years ago
• matt-kimball / toygpu
  A simple GPU on a TinyFPGA BX
  ☆81Updated 6 years ago
• SteffenReith / J1Sc
  A reimplementation of a tiny stack CPU
  ☆85Updated last year
• olofk / corescore
  CoreScore
  ☆158Updated 6 months ago
• MJoergen / HyperRAM
  Portable HyperRAM controller
  ☆56Updated 7 months ago
• tomverbeure / mr1
  MR1 formally verified RISC-V CPU
  ☆53Updated 6 years ago
• mattvenn / vga-clock
  Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
  ☆62Updated 3 years ago
• abnoname / iceZ0mb1e
  FPGA 8-Bit TV80 SoC for Lattice iCE40 with complete open-source toolchain flow using yosys and SDCC
  ☆58Updated 2 years ago
• hamsternz / emulate-risc-v
  A very simple RISC-V ISA emulator.
  ☆38Updated 4 years ago
• no2fpga / no2usb
  Nitro USB FPGA core
  ☆87Updated last year