lxp32 / lxp32-cpuLinks
A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
☆65Updated 6 months ago
Alternatives and similar repositories for lxp32-cpu
Users that are interested in lxp32-cpu are comparing it to the libraries listed below
Sorting:
- 5-stage RISC-V CPU, originally developed for RISCBoy☆35Updated 2 years ago
- SoftCPU/SoC engine-V☆55Updated 9 months ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆70Updated 3 years ago
- Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker☆103Updated 2 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆81Updated 5 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆63Updated 6 years ago
- Using VexRiscv without installing Scala☆39Updated 4 years ago
- Example Verilog code for Ulx3s☆41Updated 3 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆92Updated 7 years ago
- Portable HyperRAM controller☆61Updated last year
- Featherweight RISC-V implementation☆53Updated 3 years ago
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- Reusable Verilog 2005 components for FPGA designs☆48Updated last week
- A reimplementation of a tiny stack CPU☆85Updated 2 years ago
- A very simple RISC-V ISA emulator.☆38Updated 5 years ago
- ☆71Updated last year
- FPGA optimized RISC-V (RV32IM) implemenation☆34Updated 5 years ago
- Nitro USB FPGA core☆85Updated last year
- LatticeMico32 soft processor☆107Updated 11 years ago
- Miscellaneous ULX3S examples (advanced)☆81Updated 5 months ago
- Documenting the Anlogic FPGA bit-stream format.☆88Updated 2 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆69Updated 7 years ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆62Updated 4 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆97Updated 5 years ago
- This repository contains small example designs that can be used with the open source icestorm flow.☆154Updated 4 years ago
- MR1 formally verified RISC-V CPU☆54Updated 7 years ago
- Doom classic port to lightweight RISC‑V☆101Updated 3 years ago
- OpenSPARC-based SoC☆74Updated 11 years ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆125Updated 9 years ago
- Spen's Official OpenOCD Mirror☆51Updated 9 months ago