Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator
☆12Aug 26, 2023Updated 2 years ago
Alternatives and similar repositories for EE405-Advanced-Digital-Systems-Design
Users that are interested in EE405-Advanced-Digital-Systems-Design are comparing it to the libraries listed below
Sorting:
- Superscalar Out-of-Order NPU Design on FPGA☆11May 17, 2024Updated last year
- Matrix multiplication accelerator on ZYNQ SoC.☆12Apr 29, 2025Updated 10 months ago
- ☆11Jun 28, 2020Updated 5 years ago
- ☆16Jul 1, 2024Updated last year
- A small Neural Network Processor for Edge devices.☆16Nov 22, 2022Updated 3 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆17Sep 2, 2023Updated 2 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆21Jan 17, 2026Updated last month
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Dec 10, 2022Updated 3 years ago
- Matrix Multiplication in Hardware☆16Jun 3, 2020Updated 5 years ago
- ☆24May 26, 2022Updated 3 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆23May 20, 2019Updated 6 years ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆33Aug 13, 2024Updated last year
- matrix-coprocessor for RISC-V☆31Feb 27, 2026Updated last week
- Domain-Specific Architecture Generator 2☆22Oct 2, 2022Updated 3 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆22Jan 31, 2020Updated 6 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆37Dec 22, 2023Updated 2 years ago
- RoCEv2 hardware implementation in Bluespec SystemVerilog☆36Feb 26, 2026Updated last week
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆29Feb 6, 2023Updated 3 years ago
- vector accelerating unit☆35Dec 1, 2020Updated 5 years ago
- ☆38Oct 21, 2025Updated 4 months ago
- ☆31Aug 8, 2020Updated 5 years ago
- FPGA based Vision Transformer accelerator (Harvard CS205)☆151Feb 11, 2025Updated last year
- Pipelined FFT/IFFT 256 points processor☆10Jul 17, 2014Updated 11 years ago
- RV64GC Linux Capable RISC-V Core☆54Oct 20, 2025Updated 4 months ago
- Build a SystemVerilog Environment for an ALU, using OOP testbench components as; stimulus generator, driver, monitor, scoreboard. ALU was…☆10Mar 4, 2023Updated 3 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆14Mar 26, 2024Updated last year
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆81Updated this week
- ☆29Oct 4, 2017Updated 8 years ago
- A scientific graphing library for QtQuick☆14Feb 24, 2026Updated last week
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- A python tool that converts IBIS models to SPICE models☆13Oct 30, 2025Updated 4 months ago
- This is the repository containing the implementation of sparse dense matrix multiplication for the matrix dimension of 560 x 560.☆10Jul 7, 2021Updated 4 years ago
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆14Jan 4, 2019Updated 7 years ago
- FPGA Low latency 10GBASE-R PCS☆12May 23, 2023Updated 2 years ago
- Welcome to CV-PCL Viewer! This software has simple image and video processing functions, as well as the ability to visualize point cloud …☆16Jul 20, 2024Updated last year
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆11Jun 3, 2019Updated 6 years ago
- ☆11Mar 14, 2023Updated 2 years ago
- ☆43Mar 31, 2025Updated 11 months ago
- Convolutional Neural Network in C (for educational purposes)☆30Jan 18, 2021Updated 5 years ago