stellagarden / EE405-Advanced-Digital-Systems-DesignLinks
Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator
☆12Updated 2 years ago
Alternatives and similar repositories for EE405-Advanced-Digital-Systems-Design
Users that are interested in EE405-Advanced-Digital-Systems-Design are comparing it to the libraries listed below
Sorting:
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- ☆37Updated 6 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- A small Neural Network Processor for Edge devices.☆13Updated 2 years ago
- ☆15Updated 3 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆64Updated last week
- HLS for Networks-on-Chip☆36Updated 4 years ago
- Template for project1 TPU☆19Updated 4 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆14Updated 3 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- ☆30Updated 5 years ago
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆20Updated 2 weeks ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆15Updated last year
- RTL code of some arbitration algorithm☆14Updated 6 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆23Updated last year
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆16Updated 2 years ago
- xkDLA:XinKai Deep Learning Accelerator (RTL)☆39Updated last year
- Hardware accelerator for convolutional neural networks☆57Updated 3 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆31Updated 4 years ago
- ☆14Updated 2 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆36Updated 3 years ago
- A systolic array matrix multiplier☆27Updated 6 years ago
- eyeriss-chisel3☆41Updated 3 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Updated 6 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- ☆10Updated 5 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆11Updated 5 years ago