Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator
☆12Aug 26, 2023Updated 2 years ago
Alternatives and similar repositories for EE405-Advanced-Digital-Systems-Design
Users that are interested in EE405-Advanced-Digital-Systems-Design are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆11Jun 28, 2020Updated 5 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Dec 10, 2022Updated 3 years ago
- Neuromorphic ASIC with 96 neurons on Tiny Tapeout 7☆11May 25, 2024Updated last year
- Matrix multiplication accelerator on ZYNQ SoC.☆12Apr 29, 2025Updated 11 months ago
- ☆25May 26, 2022Updated 3 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- matrix-coprocessor for RISC-V☆31Feb 27, 2026Updated last month
- Superscalar Out-of-Order NPU Design on FPGA☆13May 17, 2024Updated last year
- Build a SystemVerilog Environment for an ALU, using OOP testbench components as; stimulus generator, driver, monitor, scoreboard. ALU was…☆10Mar 4, 2023Updated 3 years ago
- An Open-Source Processor for Accelerating Spiking Neural Network☆12Sep 30, 2022Updated 3 years ago
- Replacement SSD for Benq S6☆13Dec 24, 2021Updated 4 years ago
- vector accelerating unit☆35Dec 1, 2020Updated 5 years ago
- ☆16Jul 1, 2024Updated last year
- A python tool that converts IBIS models to SPICE models☆15Oct 30, 2025Updated 5 months ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆22Jan 31, 2020Updated 6 years ago
- Serverless GPU API endpoints on Runpod - Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- A small Neural Network Processor for Edge devices.☆18Nov 22, 2022Updated 3 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆21Jan 17, 2026Updated 3 months ago
- A low power platform based on X-HEEP and integrating the ESL-CGRA☆18Nov 12, 2025Updated 5 months ago
- RV64GC Linux Capable RISC-V Core☆57Oct 20, 2025Updated 5 months ago
- Matrix Multiplication in Hardware☆16Jun 3, 2020Updated 5 years ago
- Domain-Specific Architecture Generator 2☆23Oct 2, 2022Updated 3 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆18Sep 2, 2023Updated 2 years ago
- MLSys 2021 paper: MicroRec: efficient recommendation inference by hardware and data structure solutions☆19May 26, 2021Updated 4 years ago
- Floating-point matrix multiplication implementation (arbitrary precision)☆17Aug 3, 2021Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆111Mar 26, 2026Updated 3 weeks ago
- ☆39Oct 21, 2025Updated 5 months ago
- Notebooks for Deep Learning course (CE719) TA sessions - Sharif University of Technology☆14Jul 10, 2021Updated 4 years ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆20Nov 9, 2025Updated 5 months ago
- The basic code for transmitting and recieving data.☆23Jan 23, 2024Updated 2 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆45Jun 24, 2022Updated 3 years ago
- MINT, Multiplier-less INTeger Quantization for Energy Efficient Spiking Neural Networks, ASP-DAC 2024, Nominated for Best Paper Award☆16Apr 12, 2024Updated 2 years ago
- This is the repository containing the implementation of sparse dense matrix multiplication for the matrix dimension of 560 x 560.☆10Jul 7, 2021Updated 4 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆18Jul 9, 2024Updated last year
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Petri Net Simulator program☆10Nov 27, 2017Updated 8 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆82Mar 14, 2026Updated last month
- Simodense: a RISC-V softcore for custom SIMD instructions☆17Feb 16, 2026Updated 2 months ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆25May 20, 2019Updated 6 years ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.☆34Aug 28, 2025Updated 7 months ago
- Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis☆17Feb 16, 2024Updated 2 years ago
- RoCEv2 hardware implementation in Bluespec SystemVerilog☆36Feb 26, 2026Updated last month