klessydra / T02x
A multi-threaded microprocessor interleaving as minimum two threads, which is pin-to-pin compatible with pulpino riscy cores
☆23Updated 5 months ago
Alternatives and similar repositories for T02x:
Users that are interested in T02x are comparing it to the libraries listed below
- An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …☆46Updated 5 months ago
- A multi-threaded microprocessor interleaving as minimum three threads, which is pin-to-pin compatible with pulpino riscy cores☆14Updated 2 months ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆85Updated 5 years ago
- A fault tolerant version of the T03x core, using triple redundancy approach to ensure fault tolrance☆14Updated 5 months ago
- RISCV implementation in Verilog (RV32I spec)☆17Updated 4 years ago
- Generic Register Interface (contains various adapters)☆106Updated 4 months ago
- ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.☆29Updated this week
- CDL Hardware implementations; BBC microcomputer, RISC-V (numerous), frame buffers, JTAG, etc☆16Updated 4 years ago
- pulp_soc is the core building component of PULP based SoCs☆79Updated last week
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 8 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆42Updated 3 weeks ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆140Updated 3 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆27Updated last year
- Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations☆70Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆67Updated 10 months ago
- A RISC-V Core (RV32I) written in Chisel HDL☆100Updated 8 months ago
- MR1 formally verified RISC-V CPU☆54Updated 6 years ago
- The multi-core cluster of a PULP system.☆69Updated this week
- RiscyOO: RISC-V Out-of-Order Processor☆154Updated 4 years ago
- ☆33Updated last month
- Verilog Modules and Python Scripts for Creating IP Core Build Directories☆29Updated last year
- ☆82Updated this week
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- ☆15Updated 4 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆80Updated 9 months ago
- RISC-V Core Local Interrupt Controller (CLINT)☆25Updated last year
- RISC5Verilog for Pipistrello using lpddr memory☆13Updated 4 years ago
- Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop☆79Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆60Updated 5 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆73Updated this week