Alternatives and similar repositories for T02x

Users that are interested in T02x are comparing it to the libraries listed below

• klessydra / T13x
  An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …
  ☆45Updated last year
• klessydra / T03x
  A multi-threaded microprocessor interleaving as minimum three threads, which is pin-to-pin compatible with pulpino riscy cores
  ☆19Updated 6 months ago
• cornell-brg / lizard
  Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL
  ☆91Updated 6 years ago
• zxmarcos / riscado-v
  RISCV implementation in Verilog (RV32I spec)
  ☆17Updated 2 months ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆170Updated 5 years ago
• klessydra / F03x
  A fault tolerant version of the T03x core, using triple redundancy approach to ensure fault tolrance
  ☆16Updated last year
• tomverbeure / mr1
  MR1 formally verified RISC-V CPU
  ☆56Updated 7 years ago
• rafaelcalcada / rvx
  RISC-V microcontroller for embedded and FPGA applications
  ☆190Updated this week
• SonalPinto / kronos
  Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations
  ☆77Updated 2 years ago
• stevehoover / RISC-V_MYTH_Workshop
  Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop
  ☆97Updated 10 months ago
• carlosedp / chiselv
  A RISC-V Core (RV32I) written in Chisel HDL
  ☆106Updated 2 months ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆135Updated 2 months ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆154Updated last year
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆111Updated 3 weeks ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆255Updated last year
• atthecodeface / cdl_hardware
  CDL Hardware implementations; BBC microcomputer, RISC-V (numerous), frame buffers, JTAG, etc
  ☆17Updated 5 years ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆79Updated 2 months ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆82Updated 10 months ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆80Updated last year
• stevehoover / warp-v
  WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
  ☆243Updated 8 months ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆194Updated 4 months ago
• Domipheus / RPU
  Basic RISC-V CPU implementation in VHDL.
  ☆172Updated 5 years ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.
  ☆38Updated last week
• pulp-platform / carfield
  A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …
  ☆117Updated 6 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆127Updated 6 months ago
• manish-kj / PACoGen
  PACoGen: Posit Arithmetic Core Generator
  ☆76Updated 6 years ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆128Updated 3 months ago
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆50Updated 2 months ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆405Updated 7 months ago
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆228Updated 2 years ago