jm2000 / RISCV-FPULinks
Basic floating-point components for RISC-V processors
☆10Updated 7 years ago
Alternatives and similar repositories for RISCV-FPU
Users that are interested in RISCV-FPU are comparing it to the libraries listed below
Sorting:
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆37Updated 2 years ago
- YSYX RISC-V Project NJU Study Group☆16Updated 5 months ago
- General Purpose AXI Direct Memory Access☆50Updated last year
- verification of simple axi-based cache☆18Updated 6 years ago
- ☆20Updated 2 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆11Updated 2 years ago
- ☆16Updated 6 years ago
- ☆33Updated 6 years ago
- ☆12Updated 8 years ago
- ☆28Updated 4 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆12Updated 2 years ago
- A Direct Memory Access Controller (DMAC) with AHB-lite bus interface☆13Updated 8 months ago
- Design and UVM-TB of RISC -V Microprocessor☆20Updated 11 months ago
- [UNRELEASED] FP div/sqrt unit for transprecision☆22Updated last year
- SystemVerilog Functional Coverage for RISC-V ISA☆28Updated this week
- DUTH RISC-V Superscalar Microprocessor☆31Updated 7 months ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆24Updated 5 years ago
- Reconfigurable Binary Engine☆16Updated 4 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆30Updated last week
- Verilog and matlab implementation of tanh using Cordic algorithm☆9Updated 5 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆22Updated 3 months ago
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆22Updated 6 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- ☆49Updated 6 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆18Updated 7 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆49Updated 4 years ago
- Direct Access Memory for MPSoC☆12Updated last week
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆44Updated 8 months ago