Alternatives and similar repositories for Verilog-Floating-Point-Clock-Divider

Users that are interested in Verilog-Floating-Point-Clock-Divider are comparing it to the libraries listed below

• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆31Updated 4 years ago
• CospanDesign / nysa-verilog
  Verilog Repository for GIT
  ☆35Updated 4 years ago
• Wissance / QuickSPI
  Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
  ☆21Updated 8 years ago
• CospanDesign / vivado-ip-cores
  IP Cores that can be used within Vivado
  ☆27Updated 4 years ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆23Updated 2 years ago
• ultraembedded / core_jpeg_decoder
  HW JPEG decoder wrapper with AXI-4 DMA
  ☆36Updated 5 years ago
• KutuSystems / XilinxIP
  Xilinx IP repository
  ☆13Updated 7 years ago
• Bucknalla / ip_cores
  Verilog IP Cores & Tests
  ☆13Updated 7 years ago
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆86Updated last year
• freecores / usbhostslave
  USB 1.1 Host and Function IP core
  ☆24Updated 11 years ago
• CoreyChen922 / sata_2_host_controller
  Sata 2 Host Controller for FPGA implementation
  ☆18Updated 8 years ago
• uwemeyerbaese / DSP_with_FPGAs_ed3
  DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8
  ☆15Updated 2 months ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆48Updated 4 years ago
• kooltzh / xilinx-coe-generator
  Python script for generating Xilinx .coe files for RAM initializing
  ☆18Updated 7 years ago
• freecores / wdsp
  DSP WishBone Compatible Cores
  ☆14Updated 11 years ago
• CESNET / ofm
  Open FPGA Modules
  ☆24Updated last year
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆32Updated 9 years ago
• Elphel / eddr3
  mirror of https://git.elphel.com/Elphel/eddr3
  ☆41Updated 8 years ago
• freecores / wb_dma
  WISHBONE DMA/Bridge IP Core
  ☆18Updated 11 years ago
• siorpaes / SimpleSoC
  Very simple Cortex-M1 SoC design based on ARM DesignStart
  ☆17Updated 4 years ago
• fpgasystems / groundhog
  Groundhog - Serial ATA Host Bus Adapter
  ☆24Updated 7 years ago
• freecores / axi_master
  Generic AXI master stub
  ☆19Updated 11 years ago
• ultraembedded / core_mmc
  MMC (and derivative standards) host controller
  ☆25Updated 5 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆21Updated 2 years ago
• andrade824 / Verilog-SPI-Master
  A SPI Master IP written in verilog which is then used to output characters entered on a keypad to a serial LCD screen
  ☆19Updated 11 years ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆42Updated 4 years ago
• ericgineer / CIC
  A CIC filter implemented in Verilog
  ☆25Updated 10 years ago
• FarisHijazi / LZ4-Decompressor-Verilog
  Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language
  ☆17Updated 6 years ago
• esynr3z / usb20dev
  USB 2.0 FS Device controller IP core written in SystemVerilog
  ☆39Updated 7 years ago
• dineshannayya / usb1_host
  USB1.1 Host Controller + PHY
  ☆15Updated 4 years ago