Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter using fractional floating point division.
☆22Feb 4, 2025Updated last year
Alternatives and similar repositories for Verilog-Floating-Point-Clock-Divider
Users that are interested in Verilog-Floating-Point-Clock-Divider are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog RS232 Enhanced Synch-UART & RS232 Debugger HDL core with PC host RS232 real-time Hex-editor / viewer host utility.☆13Jan 15, 2022Updated 4 years ago
- Collaborative project to create an advanced GPU, with additional features to flesh-out the peripherals for a home-made, DIY computer.☆18Feb 26, 2023Updated 3 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆93Apr 8, 2024Updated 2 years ago
- Verilog clone of YM2149☆45Aug 2, 2026Updated last week
- Gateware for the Terasic/Arrow DECA board, to become a USB2 high speed audio interface☆22Feb 28, 2022Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- spi memory controller☆24Jan 5, 2017Updated 9 years ago
- Parsing library for BLIF netlists☆19Nov 1, 2024Updated last year
- ☆13Oct 20, 2015Updated 10 years ago
- ☆17Dec 15, 2017Updated 8 years ago
- An accelerator to which you can offload RE matching☆14Dec 22, 2024Updated last year
- In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardwar…☆21Apr 9, 2020Updated 6 years ago
- ☆36Jul 29, 2026Updated 2 weeks ago
- this repository is a project about iic master, created by gyj in second half of 2017☆18Jun 30, 2018Updated 8 years ago
- Tools to convert Kicad intermediate netlist to HDL block diagram netlist☆12Jul 21, 2016Updated 10 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Solving Bloxorz game using A* (A-star) Algorithm☆10Jan 29, 2021Updated 5 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆16Jan 22, 2025Updated last year
- Userspace DMA library for Zynq-based SoCs☆16Jan 22, 2019Updated 7 years ago
- Chisel Project for Integrating RTL code into SDAccel☆17Jan 12, 2018Updated 8 years ago
- A human detection system is developed on Matlab and FPGA: The 130x66 RGB pixels of static input image was attracted features and classifi…☆12Jan 5, 2023Updated 3 years ago
- REAPR (Reconfigurable Engine for Automata Processing) is a general-purpose framework for accelerating automata processing applications su…☆16Jun 29, 2019Updated 7 years ago
- Partial Verilog implimentation of a WiMAX OFDM Phy☆19May 28, 2012Updated 14 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆33Nov 3, 2025Updated 9 months ago
- ☆25Sep 12, 2021Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- DEC PDP-11 object file translator / linker☆14Sep 13, 2025Updated 11 months ago
- Practices related to the fundamental level of the programming language Verilog.☆13Jan 16, 2023Updated 3 years ago
- MMS CP/M 3 Source, Binaries, and related code☆16Apr 27, 2026Updated 3 months ago
- The sources of the online SpinalHDL doc☆31Jul 21, 2026Updated 3 weeks ago
- IEEE P1735 decryptor for VHDL☆40Jun 23, 2015Updated 11 years ago
- Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…☆119Jun 15, 2025Updated last year
- LXI/HTTP capture of screenshots & data from bench test kit☆13May 28, 2020Updated 6 years ago
- Cosimulation for the Rapid Open Hardware Development (ROHD) framework with other simulators☆29May 20, 2026Updated 2 months ago
- Special Function Units (SFUs) are hardware accelerators, their implementation helps improve the performance of GPUs to process some of th…☆17Sep 21, 2025Updated 10 months ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Uart module written in chisel☆13Feb 19, 2016Updated 10 years ago
- Controller for i2c EEPROM chip in Verilog for Mojo FPGA board☆27Mar 9, 2016Updated 10 years ago
- HDL and software samples for interfacing the XEM7320 with various SYZYGY peripherals.☆13Nov 14, 2019Updated 6 years ago
- A device to control AXIOM cameras.☆35Apr 5, 2026Updated 4 months ago
- ☆27Jun 12, 2022Updated 4 years ago
- Example projects for snickerdoodle☆29Jan 23, 2026Updated 6 months ago
- Simple demo showing how to use the ping pong FIFO☆17May 2, 2016Updated 10 years ago