BrianHGinc / Verilog-Floating-Point-Clock-Divider

Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter using fractional floating point division.
14Updated 2 years ago

Related projects

Alternatives and complementary repositories for Verilog-Floating-Point-Clock-Divider