BrianHGinc / Verilog-Floating-Point-Clock-DividerLinks
Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter using fractional floating point division.
☆20Updated 9 months ago
Alternatives and similar repositories for Verilog-Floating-Point-Clock-Divider
Users that are interested in Verilog-Floating-Point-Clock-Divider are comparing it to the libraries listed below
Sorting:
- SPI-Flash XIP Interface (Verilog)☆46Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆28Updated 4 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆36Updated 5 years ago
- Groundhog - Serial ATA Host Bus Adapter☆24Updated 7 years ago
- Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language☆17Updated 6 years ago
- ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)☆13Updated 7 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆17Updated 3 years ago
- IP Cores that can be used within Vivado☆26Updated 4 years ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆15Updated 6 years ago
- Verilog Repository for GIT☆33Updated 4 years ago
- Verilog IP Cores & Tests☆13Updated 7 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Updated 4 years ago
- A CIC filter implemented in Verilog☆23Updated 10 years ago
- Testbenches for HDL projects☆22Updated this week
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆26Updated 2 weeks ago
- Trying to learn Wishbone by implementing few master/slave devices☆13Updated 6 years ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆15Updated last week
- USB 1.1 Host and Function IP core☆24Updated 11 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆33Updated last year
- MMC (and derivative standards) host controller☆24Updated 5 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆31Updated 5 years ago
- Sata 2 Host Controller for FPGA implementation☆18Updated 8 years ago
- Open FPGA Modules☆24Updated last year
- A Python package for generating HDL wrappers and top modules for HDL sources☆39Updated last week
- USB -> AXI Debug Bridge☆40Updated 4 years ago
- Xilinx IP repository☆13Updated 7 years ago
- A 32 point radix-2 FFT module written in Verilog☆23Updated 5 years ago
- Fixed-point math library with VHDL, Python and MATLAB support☆28Updated last month
- USB Full Speed PHY☆47Updated 5 years ago