BrianHGinc / Verilog-Floating-Point-Clock-DividerLinks
Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter using fractional floating point division.
☆20Updated 8 months ago
Alternatives and similar repositories for Verilog-Floating-Point-Clock-Divider
Users that are interested in Verilog-Floating-Point-Clock-Divider are comparing it to the libraries listed below
Sorting:
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- USB1.1 Host Controller + PHY☆14Updated 4 years ago
- SPI-Flash XIP Interface (Verilog)☆45Updated 3 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Updated 4 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆30Updated last year
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆17Updated 3 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆35Updated 4 years ago
- Verilog Repository for GIT☆33Updated 4 years ago
- Sata 2 Host Controller for FPGA implementation☆18Updated 7 years ago
- MMC (and derivative standards) host controller☆24Updated 5 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago
- USB Full Speed PHY☆46Updated 5 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated last year
- USB 2.0 FS Device controller IP core written in SystemVerilog☆36Updated 6 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆30Updated 9 years ago
- Xilinx JTAG Toolchain on Digilent Arty board☆17Updated 7 years ago
- A CIC filter implemented in Verilog☆22Updated 10 years ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆15Updated 3 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆21Updated 7 years ago
- Groundhog - Serial ATA Host Bus Adapter☆24Updated 7 years ago
- USB 1.1 Host and Function IP core☆23Updated 11 years ago
- FMC card to allow interfacing Xilinx FPGA boards with Jetson TX2 or TX1 via CSI-2 camera interface☆19Updated 2 years ago
- Testbenches for HDL projects☆21Updated this week
- Collaborative project to create an advanced GPU, with additional features to flesh-out the peripherals for a home-made, DIY computer.☆16Updated 2 years ago
- Generic AXI master stub☆19Updated 11 years ago
- AHB-Lite Quad I/O SPI Flash memory controller with direct mapped cache and support for XiP☆14Updated last year
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆80Updated last year
- DSP WishBone Compatible Cores☆14Updated 11 years ago