BrianHGinc / Verilog-Floating-Point-Clock-DividerLinks
Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter using fractional floating point division.
☆20Updated 10 months ago
Alternatives and similar repositories for Verilog-Floating-Point-Clock-Divider
Users that are interested in Verilog-Floating-Point-Clock-Divider are comparing it to the libraries listed below
Sorting:
- Ethernet MAC 10/100 Mbps☆28Updated 4 years ago
- IP Cores that can be used within Vivado☆26Updated 4 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated last year
- HW JPEG decoder wrapper with AXI-4 DMA☆36Updated 5 years ago
- SPI-Flash XIP Interface (Verilog)☆46Updated 4 years ago
- Xilinx IP repository☆13Updated 7 years ago
- Sata 2 Host Controller for FPGA implementation☆18Updated 8 years ago
- USB 1.1 Host and Function IP core☆24Updated 11 years ago
- Testbenches for HDL projects☆22Updated this week
- USB1.1 Host Controller + PHY☆15Updated 4 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- Wishbone interconnect utilities☆43Updated 10 months ago
- Python script for generating Xilinx .coe files for RAM initializing☆18Updated 6 years ago
- Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language☆17Updated 6 years ago
- Verilog Repository for GIT☆33Updated 4 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆26Updated last month
- USB -> AXI Debug Bridge☆40Updated 4 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Updated 9 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆35Updated last year
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆17Updated 3 years ago
- WISHBONE Interconnect☆11Updated 8 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆41Updated 8 years ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆15Updated last month
- MMC (and derivative standards) host controller☆24Updated 5 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆17Updated 5 years ago
- Verilog IP Cores & Tests☆13Updated 7 years ago
- Universal Advanced JTAG Debug Interface☆17Updated last year
- DSP WishBone Compatible Cores☆14Updated 11 years ago
- Generic AXI master stub☆19Updated 11 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆37Updated 7 years ago