Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter using fractional floating point division.
☆22Feb 4, 2025Updated last year
Alternatives and similar repositories for Verilog-Floating-Point-Clock-Divider
Users that are interested in Verilog-Floating-Point-Clock-Divider are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Collaborative project to create an advanced GPU, with additional features to flesh-out the peripherals for a home-made, DIY computer.☆18Feb 26, 2023Updated 3 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆94Apr 8, 2024Updated 2 years ago
- Verilog clone of YM2149☆45Oct 25, 2026Updated last week
- YM-2149 / AY-3-8910 Complex Sound Generator FPGA core.☆41Jan 4, 2023Updated 3 years ago
- Parsing library for BLIF netlists☆19Nov 1, 2024Updated 2 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Gateware for the Terasic/Arrow DECA board, to become a USB2 high speed audio interface☆22Feb 28, 2022Updated 4 years ago
- Core protocol to AXI bridge☆11Sep 30, 2019Updated 7 years ago
- ☆12Oct 20, 2015Updated 11 years ago
- spi memory controller☆24Jan 5, 2017Updated 9 years ago
- A Preprocessor for Verilog HDL written in C++☆11May 26, 2012Updated 14 years ago
- 自建 chisel 工程模板☆16Jul 19, 2023Updated 3 years ago
- In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardwar…☆21Apr 9, 2020Updated 6 years ago
- PDP-8 OS/8 Handler and Disk Server☆12Jul 9, 2025Updated last year
- The repository for the 2024 IEEE Cloud Submission of OS4C☆10Oct 22, 2026Updated last week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Tools to convert Kicad intermediate netlist to HDL block diagram netlist☆12Jul 21, 2016Updated 10 years ago
- An accelerator to which you can offload RE matching☆14Dec 22, 2024Updated last year
- ☆17Dec 15, 2017Updated 8 years ago
- this repository is a project about iic master, created by gyj in second half of 2017☆18Jun 30, 2018Updated 8 years ago
- SystemVerilog AXI verification library and video-DMA IP: AXI4/Lite/Stream BFMs, triple-buffer VDMA, and multi-tap temporal VDMA with byte…☆30Jul 5, 2026Updated 3 months ago
- ☆39Oct 22, 2026Updated last week
- Userspace DMA library for Zynq-based SoCs☆16Jan 22, 2019Updated 7 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆39May 7, 2024Updated 2 years ago
- Human detection with HOG + SVM in MATLAB and Verilog, accelerated on a DE2-115 FPGA (0.757 ms, 54x faster than MATLAB)☆12Oct 16, 2026Updated 2 weeks ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Streetlight Costume☆11Jan 22, 2016Updated 10 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆16Jan 22, 2025Updated last year
- DEC PDP-11 object file translator / linker☆14Sep 4, 2026Updated last month
- Chisel Project for Integrating RTL code into SDAccel☆17Jan 12, 2018Updated 8 years ago
- SystemVerilog implementation of a Dynamically Weighted Round Robin arbiter☆14Mar 21, 2017Updated 9 years ago
- Partial Verilog implimentation of a WiMAX OFDM Phy☆19May 28, 2012Updated 14 years ago
- RTL Interview Questions☆12Mar 23, 2019Updated 7 years ago
- axi video dma ip in verilog☆11Aug 22, 2020Updated 6 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆35Nov 3, 2025Updated 11 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Projects I have worked on, and possibly wrote a blog post about.☆13Jul 6, 2016Updated 10 years ago
- LXI/HTTP capture of screenshots & data from bench test kit☆13May 28, 2020Updated 6 years ago
- - Use FPGA to implement MIPI interface; - Get command from PC through USB communication; - Decode command in FPGA☆13Jul 18, 2017Updated 9 years ago
- REAPR (Reconfigurable Engine for Automata Processing) is a general-purpose framework for accelerating automata processing applications su…☆16Jun 29, 2019Updated 7 years ago
- A simple flutter application using dart ffi and C++ class☆12Dec 21, 2020Updated 5 years ago
- Uart module written in chisel☆13Feb 19, 2016Updated 10 years ago
- The sources of the online SpinalHDL doc☆32Updated this week