BrianHGinc / Verilog-Floating-Point-Clock-DividerLinks
Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter using fractional floating point division.
☆20Updated 4 months ago
Alternatives and similar repositories for Verilog-Floating-Point-Clock-Divider
Users that are interested in Verilog-Floating-Point-Clock-Divider are comparing it to the libraries listed below
Sorting:
- USB 1.1 Host and Function IP core☆23Updated 10 years ago
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- SPI-Flash XIP Interface (Verilog)☆38Updated 3 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- PCI bridge☆18Updated 10 years ago
- Wishbone interconnect utilities☆41Updated 3 months ago
- Xilinx IP repository☆13Updated 7 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 4 years ago
- Sata 2 Host Controller for FPGA implementation☆17Updated 7 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆78Updated last year
- USB -> AXI Debug Bridge☆39Updated 4 years ago
- Verilog Repository for GIT☆33Updated 4 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆27Updated 11 months ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆33Updated 5 years ago
- DSP WishBone Compatible Cores☆13Updated 10 years ago
- Verilog IP Cores & Tests☆13Updated 7 years ago
- Harmon Instruments FIFO to PCI Express interface☆11Updated 4 years ago
- Testbenches for HDL projects☆18Updated this week
- USB Full Speed PHY☆44Updated 5 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆36Updated 6 years ago
- AHB-Lite Quad I/O SPI Flash memory controller with direct mapped cache and support for XiP☆12Updated last year
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆26Updated 3 months ago
- WISHBONE Interconnect☆11Updated 7 years ago
- ULPI Link Wrapper (USB Phy Interface)☆27Updated 5 years ago
- FMC card to allow interfacing Xilinx FPGA boards with Jetson TX2 or TX1 via CSI-2 camera interface☆17Updated 2 years ago
- ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)☆12Updated 6 years ago
- A SPI Master IP written in verilog which is then used to output characters entered on a keypad to a serial LCD screen☆19Updated 10 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆34Updated last year
- AXI-4 RAM Tester Component☆17Updated 4 years ago