Swingfal1 / booth_multiplier_radix_4
Verilog program
☆12Updated 4 years ago
Alternatives and similar repositories for booth_multiplier_radix_4:
Users that are interested in booth_multiplier_radix_4 are comparing it to the libraries listed below
- ☆25Updated 4 years ago
- tpu-systolic-array-weight-stationary☆20Updated 3 years ago
- ☆60Updated 6 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆14Updated 3 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆73Updated 3 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆27Updated 4 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆21Updated 3 years ago
- ☆27Updated 5 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆40Updated 5 months ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆85Updated 4 years ago
- ☆19Updated last year
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆36Updated 2 years ago
- eyeriss-chisel3☆40Updated 2 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆11Updated 4 years ago
- A verilog implementation for Network-on-Chip☆71Updated 6 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆27Updated 3 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆45Updated 4 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆65Updated last year
- achieve softmax in PYNQ with heterogeneous computing.☆61Updated 6 years ago
- 3×3脉动阵列乘法器☆36Updated 5 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆27Updated last year
- Convolutional Neural Network Implemented in Verilog for System on Chip☆26Updated 5 years ago
- 使用FPGA实现CNN模型☆13Updated 5 years ago
- ☆9Updated 4 years ago
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例,并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆23Updated last year
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆10Updated 3 years ago
- ☆99Updated 4 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆136Updated 5 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆14Updated 5 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆56Updated 5 months ago