double_fpu_verilog
☆21Jul 17, 2014Updated 12 years ago
Alternatives and similar repositories for double_fpu
Users that are interested in double_fpu are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- For CPU experiment☆14Feb 23, 2021Updated 5 years ago
- Basic floating-point components for RISC-V processors☆69Dec 4, 2019Updated 6 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 12 years ago
- Basic floating-point components for RISC-V processors☆12Aug 13, 2017Updated 8 years ago
- Generic AHB master stub☆12Jul 17, 2014Updated 12 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Pipelined FFT/IFFT 64 points processor☆11Jul 17, 2014Updated 12 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Dec 26, 2022Updated 3 years ago
- Theia: ray graphic processing unit☆20Jul 17, 2014Updated 12 years ago
- ☆30May 11, 2021Updated 5 years ago
- Bluespec H.264 Decoder☆12Jul 17, 2014Updated 12 years ago
- Zet - The x86 (IA-32) open implementation☆23Jul 17, 2014Updated 12 years ago
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆19Dec 12, 2025Updated 7 months ago
- [UNRELEASED] FP div/sqrt unit for transprecision☆27Jul 16, 2026Updated last week
- ASIC Design of the openSPARC Floating Point Unit☆17Mar 13, 2017Updated 9 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- PS2 interface☆18Dec 4, 2017Updated 8 years ago
- WISHBONE Builder☆15Sep 10, 2016Updated 9 years ago
- ☆26Feb 26, 2024Updated 2 years ago
- Verification of Ethernet Switch System Verilog☆12Oct 21, 2016Updated 9 years ago
- Binomial model☆12Aug 28, 2019Updated 6 years ago
- 标准视频时序生成器☆10Feb 9, 2020Updated 6 years ago
- Pipelined FFT/IFFT 256 points processor☆10Jul 17, 2014Updated 12 years ago
- Verilog-Based-NoC-Simulator☆12May 4, 2016Updated 10 years ago
- Hardware Division Units☆10Jul 17, 2014Updated 12 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- The old libjpeg☆12Jul 30, 2015Updated 10 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- Advanced Peripheral Bus (APB) UVM testbench project☆10Apr 9, 2017Updated 9 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆16Jan 22, 2025Updated last year
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆38Dec 24, 2024Updated last year
- ☆13Apr 16, 2022Updated 4 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆25Jul 14, 2020Updated 6 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- USB 1.1 PHY☆11Jul 17, 2014Updated 12 years ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated 2 years ago
- Y80e - Z80/Z180 compatible processor extended by eZ80 instructions☆22Jul 17, 2014Updated 12 years ago
- UVM testbench for verifying the Pulpino SoC☆14Mar 23, 2020Updated 6 years ago
- Direct Access Memory for MPSoC☆13Jun 16, 2026Updated last month
- ☆14Jul 16, 2026Updated last week
- Video compression systems☆24Jul 17, 2014Updated 12 years ago