anikau31 / systemc-clangLinks
This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
☆86Updated 11 months ago
Alternatives and similar repositories for systemc-clang
Users that are interested in systemc-clang are comparing it to the libraries listed below
Sorting:
- Public repository for PySysC, (From SC Common Practices Subgroup)☆53Updated last year
- A SystemVerilog source file pickler.☆60Updated 10 months ago
- SoCRocket - Core Repository☆38Updated 8 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 2 months ago
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆114Updated this week
- An open source high level synthesis (HLS) tool built on top of LLVM☆124Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 7 months ago
- Open source RTL simulation acceleration on commodity hardware☆29Updated 2 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆61Updated 2 weeks ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last week
- A GPU acceleration flow for RTL simulation with batch stimulus☆113Updated last year
- ☆97Updated last year
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated 3 months ago
- Next generation CGRA generator☆114Updated this week
- Constrained random stimuli generation for C++ and SystemC☆52Updated last year
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆90Updated 3 weeks ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- RISC-V Virtual Prototype☆44Updated 3 years ago
- A library and command-line tool for querying a Verilog netlist.☆27Updated 3 years ago
- Mirror of tachyon-da cvc Verilog simulator☆47Updated 2 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆38Updated 2 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆69Updated 8 months ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆111Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆119Updated 2 months ago
- For contributions of Chisel IP to the chisel community.☆65Updated 10 months ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆88Updated last year