anikau31 / systemc-clangLinks
This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
☆88Updated last year
Alternatives and similar repositories for systemc-clang
Users that are interested in systemc-clang are comparing it to the libraries listed below
Sorting:
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆129Updated last week
- SoCRocket - Core Repository☆38Updated 8 years ago
- Public repository for PySysC, (From SC Common Practices Subgroup)☆54Updated 2 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 7 months ago
- Open source RTL simulation acceleration on commodity hardware☆34Updated 2 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆117Updated last year
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Updated 3 weeks ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated 3 weeks ago
- ☆31Updated 2 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆127Updated last year
- ☆113Updated 2 months ago
- A SystemVerilog source file pickler.☆60Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆69Updated 11 months ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 3 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆98Updated last month
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆88Updated 4 years ago
- Next generation CGRA generator☆118Updated this week
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆55Updated 5 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆41Updated 2 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆122Updated 4 years ago
- RISC-V Virtual Prototype☆46Updated 4 years ago
- A modeling library with virtual components for SystemC and TLM simulators☆179Updated last week
- ☆68Updated 3 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆52Updated 5 years ago
- high-performance RTL simulator☆186Updated last year
- Constrained random stimuli generation for C++ and SystemC☆53Updated 2 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago
- Project repo for the POSH on-chip network generator☆52Updated 10 months ago
- (System)Verilog to Chisel translator☆116Updated 3 years ago