Artifact for Oaken: Fast and Efficient LLM Serving with Online-Offline Hybrid KV Cache Quantization
☆18May 9, 2025Updated last year
Alternatives and similar repositories for oaken
Users that are interested in oaken are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Tender: Accelerating Large Language Models via Tensor Decompostion and Runtime Requantization (ISCA'24)☆34Jul 4, 2024Updated 2 years ago
- Accelerator RTL inspired by VEGETA [HPCA'23] and MicroScopiQ [ISCA'25]☆15Nov 11, 2025Updated 9 months ago
- ☆12Jul 2, 2024Updated 2 years ago
- ☆41Oct 21, 2025Updated 10 months ago
- ☆29Apr 15, 2025Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆164Jun 24, 2024Updated 2 years ago
- DreamRAM: A Fine-Grained Configurable Design Space Modeling Tool for Custom 3D Die-Stacked DRAM☆17Aug 19, 2026Updated last week
- [ASPLOS 2026] M2XFP: A Metadata-Augmented Microscaling Data Format for Efficient Low-bit Quantization.☆16Jan 29, 2026Updated 6 months ago
- A Full-System Framework for Simulating NDP devices from Caches to DRAM☆21Jan 12, 2024Updated 2 years ago
- A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0☆72Jul 22, 2025Updated last year
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆27Aug 23, 2021Updated 5 years ago
- Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…☆26Mar 29, 2025Updated last year
- ☆20Aug 6, 2026Updated 2 weeks ago
- Artifact for "DX100: A Programmable Data Access Accelerator for Indirection (ISCA 2025)" paper☆19Nov 6, 2025Updated 9 months ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆115Apr 26, 2025Updated last year
- A bit-level sparsity-awared multiply-accumulate process element.☆20Jul 9, 2024Updated 2 years ago
- ☆63Oct 14, 2025Updated 10 months ago
- Composable HLS library for rapid development of LLM accelerators. FlexLLM enables spatial-temporal hybrid architectures, with parameteriz…☆28Aug 17, 2026Updated last week
- ☆267Oct 24, 2025Updated 10 months ago
- Artifact material for [HPCA 2025] #2108 "UniNDP: A Unified Compilation and Simulation Tool for Near DRAM Processing Architectures"☆63Sep 1, 2025Updated 11 months ago
- ☆23Jun 25, 2025Updated last year
- FSA: Fusing FlashAttention within a Single Systolic Array☆194Apr 15, 2026Updated 4 months ago
- ☆158Jul 19, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆90Apr 26, 2026Updated 4 months ago
- ☆24Apr 3, 2026Updated 4 months ago
- PyTorchSim is a Comprehensive, Fast, and Accurate NPU Simulation Framework☆137Aug 5, 2026Updated 3 weeks ago
- Fast Emulation of Approximate DNN Accelerators in PyTorch☆31Feb 23, 2024Updated 2 years ago
- A tool for decomposing DRAM address mapping into component-level functions☆16Jun 12, 2025Updated last year
- CGRA framework with vectorization support.☆52Updated this week
- 🎓Automatically Update circult-eda-mlsys-tinyml Papers Daily using Github Actions (Update Every 8th hours)☆10Updated this week
- TeLLMe: An Efficient End-to-End Ternary LLM Prefill and Decode Accelerator with Table-Lookup Matmul on Edge FPGAs [FPGA2026]☆34Mar 11, 2026Updated 5 months ago
- KV cache compression via sparse coding☆18Oct 26, 2025Updated 9 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning☆138Aug 27, 2024Updated last year
- MetaAttention: A Unified and Performant Attention Framework Across Hardware Backends(PPoPP'26)☆17Aug 6, 2026Updated 2 weeks ago
- Here are some implementations of basic hardware units in RTL language (verilog for now), which can be used for area/power evaluation and …☆15Aug 25, 2023Updated 3 years ago
- ☆10Dec 26, 2023Updated 2 years ago
- A PYNQ overlay demonstrating the Xilinx RFSoC SD-FEC☆13Jun 29, 2022Updated 4 years ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆77Dec 29, 2025Updated 7 months ago
- [FCCM 2026] Official repository for LUT-LLM: Efficient Language Model Inference with Memory-based Computation on FPGAs☆44Apr 12, 2026Updated 4 months ago