jetafese / btor2mlir
Bᴛᴏʀ2MLIR: A Format and Toolchain for Hardware Verification
☆10Updated 2 weeks ago
Related projects ⓘ
Alternatives and complementary repositories for btor2mlir
- BTOR2 MLIR project☆16Updated 10 months ago
- ☆11Updated 3 years ago
- A high-performance implementation of the IC3/PDR algorithm in Rust.☆16Updated this week
- PolyGen is a code generator for the polyhedral model, written and proved in Coq.☆10Updated 4 years ago
- ☆12Updated last year
- Using e-graphs to synthesize netlists from boolean logic.☆14Updated last year
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆25Updated 4 months ago
- ☆11Updated 4 years ago
- ☆15Updated 2 years ago
- FPGA synthesis tool powered by program synthesis☆38Updated this week
- compiling DSLs to high-level hardware instructions☆21Updated 2 years ago
- Verilog AST☆19Updated 11 months ago
- ☆14Updated 2 years ago
- ☆14Updated 4 months ago
- ILA Model Database☆20Updated 4 years ago
- Logic Synthesis System from UC Berkeley (Unofficial Distribution)☆15Updated 5 years ago
- QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification☆14Updated 8 years ago
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 3 years ago
- SMTSampler: Efficient Stimulus Generation from Complex SMT Constraints☆24Updated 5 years ago
- AMulet 2. - A better AIG Multiplier Examination Tool☆20Updated 2 years ago
- ☆41Updated 3 years ago
- ☆15Updated last year
- CoreIR Symbolic Analyzer☆61Updated 4 years ago
- ☆14Updated 3 years ago
- Python version of tools to work with AIG formatted files☆10Updated 6 months ago
- ☆12Updated 2 years ago
- ☆16Updated 5 months ago
- ☆9Updated 9 years ago
- Automatically generate a compiler using equality saturation☆26Updated 7 months ago
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆22Updated 2 months ago