Alternatives and similar repositories for btor2mlir

Users that are interested in btor2mlir are comparing it to the libraries listed below

• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆26Updated last year
• iscas-tis / CHA
  ☆19Updated last year
• gipsyh / rIC3-HWMCC24
  rIC3 model checker for Hardware Model Checking Competition 2024(HWMCC'24) submission
  ☆12Updated 2 weeks ago
• gussmith23 / lakeroad
  FPGA synthesis tool powered by program synthesis
  ☆51Updated last week
• UCSBarchlab / owl
  Control Logic Synthesis: Drawing the Rest of the OWL
  ☆11Updated last year
• CoriolisSP / FuzzBtor2
  Random Generator of Btor2 Files
  ☆10Updated last year
• opencompl / mlir-fuzz
  A enumerator for MLIR, relying on the information given by IRDL.
  ☆19Updated this week
• mit-plv / hemiola
  A Coq framework to support structural design and proof of hardware cache-coherence protocols
  ☆14Updated 3 years ago
• Ekdohibs / PolyGen
  PolyGen is a code generator for the polyhedral model, written and proved in Coq.
  ☆10Updated 4 years ago
• aqjune / mlir-tv
  A translation validation framework for MLIR
  ☆87Updated 3 months ago
• mgudemann / iimc
  ☆13Updated 7 years ago
• lijwen2748 / simplecar
  ☆15Updated 2 years ago
• diffblue / hw-cbmc
  The HW-CBMC and EBMC Model Checkers for Verilog
  ☆79Updated this week
• uwplse / rake
  compiling DSLs to high-level hardware instructions
  ☆22Updated 2 years ago
• ymanerka / rtlcheck
  RTLCheck
  ☆22Updated 6 years ago
• iscas-tis / ChiRVFormal
  Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.
  ☆14Updated last month
• hwmcc / btor2tools
  A generic parser and tool package for the BTOR2 format.
  ☆41Updated 2 months ago
• cucapra / patronus
  work in progress, playing around with btor2 in rust
  ☆11Updated 3 weeks ago
• vegaluisjose / vast
  Verilog AST
  ☆21Updated last year
• RafaelTupynamba / SMTSampler
  SMTSampler: Efficient Stimulus Generation from Complex SMT Constraints
  ☆29Updated 5 years ago
• ezyang / SMT-LIB-benchmarks-pytorch-shapes
  SMT-LIB benchmarks for shape computations from deep learning models in PyTorch
  ☆17Updated 2 years ago
• gussmith23 / churchroad
  FPGA synthesis tool powered by equality saturation and program synthesis.
  ☆12Updated last week
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆73Updated 4 years ago
• mikeurbach / egg-netlist-synthesizer
  Using e-graphs to synthesize netlists from boolean logic.
  ☆14Updated last year
• stanford-centaur / pono
  Pono: A flexible and extensible SMT-based model checker
  ☆105Updated this week
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆45Updated this week
• yihozhang / relational-ematching-benchmark
  ☆16Updated 3 years ago
• lip6 / painless
  A framework to ease parallelization of sequential SAT solvers
  ☆19Updated 2 months ago
• efeslab / asplos22-hardware-debugging-artifact
  ☆12Updated last year
• muhos / ParaFROST
  A Parallel SAT Solver with GPU Accelerated Inprocessing
  ☆119Updated 2 weeks ago