Alternatives and similar repositories for cluster_interconnect

Users that are interested in cluster_interconnect are comparing it to the libraries listed below

• hyoukjun / OpenSMART
  Public release
  ☆58Updated 6 years ago
• vinodsake / Last-Level-Cache-Simulator
  ☆13Updated 8 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆37Updated 4 years ago
• chipsalliance / aib-protocols
  ☆28Updated last year
• muzafferkal / axi-bfm
  AXI3 Bus Functional Models (Initiator & Target)
  ☆29Updated 2 years ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆42Updated 4 years ago
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆70Updated 5 years ago
• hyoukjun / microswitch-noc
  ☆28Updated 6 years ago
• jessebarreto / NetworkOnChip
  Development of a Network on Chip Simulation using SystemC.
  ☆33Updated 8 years ago
• govindjeevan / Weighted-Round-Robin-Arbiter
  Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components
  ☆20Updated 7 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆61Updated last year
• pulp-platform / ace
  ☆19Updated last month
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 5 years ago
• pulp-platform / axi2apb
  ☆21Updated 5 years ago
• pulp-platform / hier-icache
  ☆13Updated 9 months ago
• pulp-platform / uvm-components
  Contains commonly used UVM components (agents, environments and tests).
  ☆31Updated 7 years ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 6 years ago
• pulp-platform / fpu_div_sqrt_mvp
  [UNRELEASED] FP div/sqrt unit for transprecision
  ☆24Updated 2 months ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆32Updated 5 months ago
• yuhsuan-t / NPU-Architecture
  CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations
  ☆19Updated 8 years ago
• kuladeepsaireddy / OpenNoc
  ☆37Updated 6 years ago
• pulp-platform / axi_llc
  ☆32Updated this week
• PacoReinaCampo / MPSoC-DMA
  Direct Access Memory for MPSoC
  ☆13Updated 2 weeks ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆32Updated last year
• ic-lab-duth / DRIM
  DUTH RISC-V Microprocessor
  ☆22Updated 11 months ago
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆54Updated 4 years ago
• jmjos / ratatoskr
  Ratatoskr NoC Simulator
  ☆28Updated 4 years ago
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆51Updated this week
• chad-q / andes-vector-riscv-dv
  Andes Vector Extension support added to riscv-dv
  ☆17Updated 5 years ago
• pulp-platform / hwpe-stream
  IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
  ☆20Updated last week