☆17Oct 28, 2025Updated 4 months ago
Alternatives and similar repositories for cluster_interconnect
Users that are interested in cluster_interconnect are comparing it to the libraries listed below
Sorting:
- A simple, scalable, source-synchronous, all-digital DDR link☆36Mar 13, 2026Updated last week
- ECE 4551: Computer Architecture☆11Nov 25, 2019Updated 6 years ago
- whatever it means☆15Updated this week
- ☆14Oct 8, 2024Updated last year
- NoC simulation using gem5 (a simple tul)☆14Mar 23, 2024Updated last year
- Manycore platform Simulation tool for NoC-based platform at a Cycle-accurate level☆12Feb 22, 2018Updated 8 years ago
- Rust support for RISC-V Platform-Level Interrupt Controller☆10Oct 13, 2022Updated 3 years ago
- An example Hardware Processing Engine☆12Feb 4, 2023Updated 3 years ago
- ☆12Sep 25, 2024Updated last year
- ☆16Sep 26, 2022Updated 3 years ago
- Simple example of how to write an Implicit GEMM Convolution in CUDA using the tensor core WMMA API and bindings for PyTorch.☆18Jun 29, 2023Updated 2 years ago
- Hardware Snappy decompressor☆11Sep 11, 2024Updated last year
- TockOS - An OS for Embedded Devices☆33May 16, 2015Updated 10 years ago
- Manycore platform Simulation tool for NoC-based platform at a Transactional Level Modeling level☆10Aug 30, 2016Updated 9 years ago
- A reliable, real-time subsystem for the Carfield SoC☆20Dec 2, 2025Updated 3 months ago
- [EXPERIMENTAL] RISC-V platform crate for Drone, an Embedded Operating System.☆12Apr 9, 2021Updated 4 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Aug 22, 2021Updated 4 years ago
- Parametric GPIO Peripheral☆12Jan 30, 2025Updated last year
- Trying to learn Wishbone by implementing few master/slave devices☆13Jan 7, 2019Updated 7 years ago
- A multi-cycle processor designed according to the instruction set(assembly language) of RISC-V using the System Verilog HDL☆20Jun 5, 2023Updated 2 years ago
- Memory Benchmark for OpenCL-supported Intel FPGAs☆11Dec 25, 2023Updated 2 years ago
- 开放验证平台NutShell Cache验证案例☆11Dec 2, 2025Updated 3 months ago
- A highly scalable framework for the performance and energy monitoring of HPC servers☆21Oct 11, 2025Updated 5 months ago
- A simple lua jit implemented in Rust for HUST-Complier principle course.☆12May 19, 2021Updated 4 years ago
- An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders☆23Jan 6, 2026Updated 2 months ago
- 恰饭网：华中科技大学系统能力竞赛团队主页☆11Jul 23, 2021Updated 4 years ago
- Original test vector of RISC-V Vector Extension☆14Mar 23, 2021Updated 4 years ago
- Artifacts for ATC '22 paper "Faster Software Packet Processing on FPGA NICs with eBPF Program Warping"☆17May 20, 2022Updated 3 years ago
- AXI-4 RAM Tester Component☆21Aug 5, 2020Updated 5 years ago
- 在RISC-V处理器上实现一个轻量级的Hypervisor。☆12Dec 25, 2020Updated 5 years ago
- Repository to show an example of how to do version control with Vivado and Xilinx SDK☆15Nov 10, 2017Updated 8 years ago
- ☆26May 31, 2023Updated 2 years ago
- High-speed real time streaming video on Zybo Z7-10☆17May 5, 2019Updated 6 years ago
- ☆40Updated this week
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆153Jan 8, 2026Updated 2 months ago
- An FPGA-CPU co-design framework for accelerating software NFs (Network Functions) with Intel DPDK☆12May 27, 2020Updated 5 years ago
- Official Intel SOCFPGA Arm-TF repository. Note: (1) A "RC" labeled branch is for internal active development use and customer early acces…☆18Feb 28, 2026Updated 3 weeks ago
- A vector processor implemented in Chisel☆21Aug 3, 2014Updated 11 years ago
- A simple cycle-accurate DaDianNao simulator☆13Mar 27, 2019Updated 6 years ago