pulp-platform / cluster_interconnectLinks
☆16Updated 2 months ago
Alternatives and similar repositories for cluster_interconnect
Users that are interested in cluster_interconnect are comparing it to the libraries listed below
Sorting:
- HLS for Networks-on-Chip☆39Updated 4 years ago
- ☆28Updated 6 years ago
- Development of a Network on Chip Simulation using SystemC.☆33Updated 8 years ago
- Public release☆58Updated 6 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆60Updated last month
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆74Updated 6 years ago
- Ratatoskr NoC Simulator☆29Updated 4 years ago
- ☆13Updated 8 years ago
- ☆33Updated last month
- Xilinx AXI VIP example of use☆43Updated 4 years ago
- ☆40Updated 6 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- SystemVerilog modules and classes commonly used for verification☆54Updated last week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆94Updated last month
- General Purpose AXI Direct Memory Access☆62Updated last year
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Updated last month
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆77Updated last month
- ☆31Updated 5 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Updated 7 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- ☆20Updated 3 weeks ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆55Updated 8 years ago
- A verilog implementation for Network-on-Chip☆79Updated 7 years ago
- CNN accelerator using NoC architecture☆17Updated 7 years ago
- ☆10Updated 3 years ago
- ☆57Updated 6 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆11Updated 5 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆21Updated last month
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆44Updated 3 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆48Updated last month