Alternatives and similar repositories for leros

Users that are interested in leros are comparing it to the libraries listed below

• schoeberl / lipsi
  Lipsi: Probably the Smallest Processor in the World
  ☆89Updated last year
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆107Updated 4 years ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆170Updated 5 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆184Updated 9 months ago
• carlosedp / chiselv
  A RISC-V Core (RV32I) written in Chisel HDL
  ☆107Updated this week
• SpinalHDL / SpinalTemplateSbt
  A basic SpinalHDL project
  ☆90Updated 5 months ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆116Updated 3 years ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆111Updated 2 years ago
• agra-uni-bremen / riscv-vp
  RISC-V Virtual Prototype
  ☆183Updated last year
• SpinalHDL / SpinalWorkshop
  Labs to learn SpinalHDL
  ☆153Updated last year
• librecores / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆67Updated 6 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆70Updated last year
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆88Updated 4 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆109Updated 4 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆99Updated last year
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆123Updated 2 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆127Updated 6 months ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆153Updated last month
• mortbopet / VSRTL
  Visual Simulation of Register Transfer Logic
  ☆110Updated 5 months ago
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆129Updated 8 months ago
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆100Updated 3 years ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆200Updated this week
• schoeberl / wildcat
  An implementation of RISC-V
  ☆47Updated last month
• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆81Updated 6 years ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆135Updated 7 years ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated last month
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆105Updated 9 months ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆238Updated last year
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆127Updated last year
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆82Updated 10 months ago