leros-dev / lerosLinks
A Tiny Processor Core
☆110Updated last month
Alternatives and similar repositories for leros
Users that are interested in leros are comparing it to the libraries listed below
Sorting:
- Lipsi: Probably the Smallest Processor in the World☆86Updated last year
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆101Updated 3 years ago
- Labs to learn SpinalHDL☆150Updated last year
- Verilog implementation of a RISC-V core☆123Updated 6 years ago
- RISC-V Virtual Prototype☆176Updated 8 months ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆179Updated 3 months ago
- A RISC-V Core (RV32I) written in Chisel HDL☆103Updated 2 weeks ago
- (System)Verilog to Chisel translator☆116Updated 3 years ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆230Updated 9 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆120Updated last month
- Chisel Learning Journey☆109Updated 2 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆160Updated 5 years ago
- Yet Another RISC-V Implementation☆96Updated 11 months ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆172Updated this week
- RISC-V Torture Test☆197Updated last year
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- ☆182Updated last year
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆174Updated last month
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆73Updated last year
- SoC based on VexRiscv and ICE40 UP5K☆159Updated 5 months ago
- educational microarchitectures for risc-v isa☆66Updated 6 years ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆57Updated last year
- Mathematical Functions in Verilog☆94Updated 4 years ago
- A basic SpinalHDL project☆88Updated last week
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆217Updated 5 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆81Updated 5 years ago
- ☆294Updated 2 weeks ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆123Updated 3 months ago