leros-dev / lerosLinks
A Tiny Processor Core
☆114Updated 4 months ago
Alternatives and similar repositories for leros
Users that are interested in leros are comparing it to the libraries listed below
Sorting:
- Lipsi: Probably the Smallest Processor in the World☆88Updated last year
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 6 months ago
- RISC-V Virtual Prototype☆179Updated 11 months ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆102Updated 4 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆123Updated 4 months ago
- Labs to learn SpinalHDL☆150Updated last year
- Chisel Learning Journey☆110Updated 2 years ago
- educational microarchitectures for risc-v isa☆67Updated 6 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆164Updated 5 years ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆235Updated 11 months ago
- A basic SpinalHDL project☆86Updated 3 months ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆190Updated this week
- Yet Another RISC-V Implementation☆98Updated last year
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- ☆189Updated last year
- 64-bit multicore Linux-capable RISC-V processor☆99Updated 6 months ago
- Verilog implementation of a RISC-V core☆128Updated 7 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆80Updated 6 years ago
- A RISC-V Core (RV32I) written in Chisel HDL☆104Updated 2 weeks ago
- Provides dot visualizations of chisel/firrtl circuits☆122Updated 2 years ago
- For contributions of Chisel IP to the chisel community.☆67Updated last year
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆101Updated this week
- Provides various testers for chisel users☆100Updated 2 years ago
- RISC-V Torture Test☆202Updated last year
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆86Updated 4 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆149Updated 2 weeks ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆76Updated last year
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆161Updated 3 years ago