bselimoglu / SoC-ZedBoard-Zynq-7000-LabsLinks
Hardware and Software Co-design implementations
☆14Updated 5 years ago
Alternatives and similar repositories for SoC-ZedBoard-Zynq-7000-Labs
Users that are interested in SoC-ZedBoard-Zynq-7000-Labs are comparing it to the libraries listed below
Sorting:
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆37Updated 4 years ago
- Repository for system verilog labs from cadence☆13Updated 5 years ago
- Ethernet MAC 10/100 Mbps☆83Updated 5 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆64Updated 5 years ago
- IP operations in verilog (simulation and implementation on ice40)☆55Updated 5 years ago
- We are aimed at making a device for shooting real-time HDR (High Dynamic Range) video using FPGA.☆32Updated 6 years ago
- Interface Protocol in Verilog☆50Updated 5 years ago
- TCL, verilog and shell scripts used while learning Cadence genus, innovus and tempus tools.☆14Updated 3 years ago
- FPGA和USB3.0桥片实现USB3.0通信☆68Updated 3 years ago
- FPGA 同步FIFO与异步FIFO☆31Updated 6 years ago
- JPEG Encoder Verilog☆76Updated 2 years ago
- Verilog SPI master and slave☆55Updated 9 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆61Updated 3 years ago
- [Course] Hands-On ZYNQ: Mastering AXI4 Bus Protocol☆18Updated 5 years ago
- An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器☆58Updated last year
- Verilog based BCH encoder/decoder☆122Updated 2 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆58Updated 4 years ago
- ☆69Updated 3 years ago
- DDR4 Simulation Project in System Verilog☆41Updated 10 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆34Updated 4 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆74Updated 2 years ago
- SDRAM controller with AXI4 interface☆94Updated 5 years ago
- An FPGA-based LZMA compressor for generic data compression. 基于FPGA的LZMA压缩器,用于通用数据压缩。☆85Updated last year
- An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …☆131Updated last year
- Generic FIFO implementation with optional FWFT☆59Updated 5 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆33Updated 5 years ago
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆130Updated 5 years ago
- USB -> AXI Debug Bridge☆39Updated 4 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- UART -> AXI Bridge☆61Updated 4 years ago