Hardware and Software Co-design implementations
☆15Dec 5, 2019Updated 6 years ago
Alternatives and similar repositories for SoC-ZedBoard-Zynq-7000-Labs
Users that are interested in SoC-ZedBoard-Zynq-7000-Labs are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…☆11Jul 19, 2022Updated 3 years ago
- FPGA with Xilinx Vitis HLS, Vivado, Vitis, and ZYNQ board. Working with HLS, Matrix Multiplier with HLS☆16Mar 1, 2021Updated 5 years ago
- A hardware implementation of a feed-forward Convolutional Neural Network called XNOR-Net which has faster execution due to the replacemen…☆17Sep 16, 2018Updated 7 years ago
- Demonstration of a video processing design for the Digilent Zybo, using Web Camera for input and VGA interface for output.☆26Aug 28, 2016Updated 9 years ago
- In this repository, I have shared the codes for designs and testbenches, Elaborated Design and Simulation Output for each block of RISC-V…☆25Aug 28, 2024Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- FPGA 百兆以太网☆12Feb 23, 2019Updated 7 years ago
- ☆35Nov 24, 2021Updated 4 years ago
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆36Apr 13, 2024Updated last year
- Social Disatancing Monitor using yolov3 and DPU HW acceleration for Xilinx adaptive computing challenge 2020☆12Feb 17, 2023Updated 3 years ago
- Convolutional Neural Network in C (for educational purposes)☆30Jan 18, 2021Updated 5 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆45Sep 26, 2023Updated 2 years ago
- [Course] Hands-On ZYNQ: Mastering AXI4 Bus Protocol☆19Feb 22, 2020Updated 6 years ago
- Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis☆17Feb 16, 2024Updated 2 years ago
- Zynq-7000 DPU TRD☆48Jul 19, 2019Updated 6 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- Numerical experiments on Jacobi SVD algorithm☆10Jun 3, 2018Updated 7 years ago
- A vision transformer based framework for classifying executable images as benign or malicious☆10Mar 19, 2024Updated 2 years ago
- ☆29Updated this week
- C语言实现封装的服务器框架,多进程+单线程+libevent+openssl+ORMSQL☆10Jul 30, 2019Updated 6 years ago
- 基于USB2.0 的数据采集卡☆21Feb 20, 2019Updated 7 years ago
- Using verilog to implement MAC (Multiply Accumulate) . Verifying it by testbench .☆15Feb 17, 2019Updated 7 years ago
- A digital Oscilloscope designed using Zedboard (Zynq7000Soc). The input signal is sample and processed using Zedboard and the sample dat…☆26Jul 30, 2020Updated 5 years ago
- Mastering FPGASIC Book☆18Oct 26, 2025Updated 5 months ago
- A Verilog implementation of a hand-written digit recognition Neural Network☆10Nov 16, 2024Updated last year
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Using Xilinx tools, the Unet architecture will be implemented and optimized for FPGA use. Some convolution-transposed conv sub-parts of t…☆18Feb 25, 2021Updated 5 years ago
- 基于FPGA的FFT☆19Feb 18, 2019Updated 7 years ago
- Global Dark Mode for ALL apps on ANY platforms.☆19Oct 3, 2023Updated 2 years ago
- ☆14Sep 27, 2022Updated 3 years ago
- A collection of Beamer samples in Persian☆16May 7, 2024Updated last year
- This repository contains the details and the code for the MIPS32 ISA based RISC Processor, which is implemented in 5 stage pipelined conf…☆17Apr 26, 2023Updated 2 years ago
- ☆12Mar 5, 2025Updated last year
- High-level synthesis (HLS) implementation of Sparse Matrix Vector Multiplication☆19Feb 17, 2022Updated 4 years ago
- FPGA Implementation of Image Processing for MNIST Dataset Based on Convolutional Neural Network Algorithm (CNN)☆11Dec 12, 2023Updated 2 years ago
- NordVPN Threat Protection Pro™ • AdTake your cybersecurity to the next level. Block phishing, malware, trackers, and ads. Lightweight app that works with all browsers.
- Experimental password store for Blackpill card utilizing usb serial and spi flash☆18Updated this week
- Implementation of the BitLinear layer from: The Era of 1-bit LLMs: All Large Language Models are in 1.58 Bits☆14Sep 11, 2024Updated last year
- ☆12Apr 9, 2018Updated 7 years ago
- ☆14Jul 12, 2023Updated 2 years ago
- FPGA digital camera controller and frame capture device in VHDL☆15Feb 11, 2013Updated 13 years ago
- ☆24Jan 4, 2026Updated 2 months ago
- Integration on PL side of Zynq7000 for PYNQ framework of common industrial devices (GPIO, I2C, SPI and UART)☆38Jul 7, 2021Updated 4 years ago