In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transfer Level (RTL) to the Graphical Data System (GDS)
☆20Aug 19, 2024Updated last year
Alternatives and similar repositories for NASSCOM-VSD-SoC-design-Program
Users that are interested in NASSCOM-VSD-SoC-design-Program are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆24Nov 11, 2025Updated 6 months ago
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆16Oct 16, 2021Updated 4 years ago
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆59Apr 13, 2024Updated 2 years ago
- This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…☆11Jul 19, 2022Updated 3 years ago
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆13Aug 26, 2024Updated last year
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- ☆14Sep 29, 2024Updated last year
- This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)☆34Nov 25, 2024Updated last year
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆54Jan 4, 2022Updated 4 years ago
- ☆17Sep 16, 2022Updated 3 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆81Nov 26, 2020Updated 5 years ago
- In this repository, I have shared the codes for designs and testbenches, Elaborated Design and Simulation Output for each block of RISC-V…☆27Aug 28, 2024Updated last year
- This repository aims to capture the works done in 5-day workshop of Adavance Physical Design using OpenLANE/SkyWater130. The workshop hel…☆22Jul 5, 2021Updated 4 years ago
- ☆14Apr 13, 2025Updated last year
- Implementation of RISC-V RV32I☆30Aug 30, 2022Updated 3 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- opensource EDA tool flor VLSI design☆37Sep 17, 2023Updated 2 years ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆29Apr 29, 2024Updated 2 years ago
- Examples of the TCL Scripts for different purposes and for VLSI Physical Design are provided here for your reference☆36Dec 30, 2022Updated 3 years ago
- 5 stage pipeline implementation of RISC-V 32I Processor.☆10Nov 27, 2024Updated last year
- Semiconductor Packaging Fundamentals☆29May 19, 2025Updated last year
- Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop☆98Apr 25, 2026Updated last month
- Design Verification Engineer interview preparation guide.☆50Jul 20, 2025Updated 10 months ago
- Learning Path: RISC-V & Advanced Edge AI on SiFive FE310-G002 SoC | 32-bit RISC-V | 320 MHz | 16KB L1 Instruction Cache | 128Mbit (16MB) …☆12Sep 18, 2025Updated 8 months ago
- ☆16May 23, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Apr 18, 2019Updated 7 years ago
- AMD Xilinx University Program Vivado tutorial☆49Feb 13, 2023Updated 3 years ago
- A vision transformer based framework for classifying executable images as benign or malicious☆10Mar 19, 2024Updated 2 years ago
- This repository contains all the information included in the beginner SoC/physical design using open-source EDA tools organized by VLSI S…☆14Mar 7, 2021Updated 5 years ago
- ☆16Jul 30, 2021Updated 4 years ago
- ☆15Dec 2, 2021Updated 4 years ago
- Auto tagging of stack overflow questions. Used dataset: https://www.kaggle.com/stackoverflow/stacksample☆11May 25, 2020Updated 6 years ago
- VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.☆32Jul 21, 2025Updated 10 months ago
- An FPGA design for simulating biological neurons☆18Jul 5, 2024Updated last year
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- A Simple Flask App to interact with your Machine Translation Model☆13Feb 26, 2020Updated 6 years ago
- Using Xilinx tools, the Unet architecture will be implemented and optimized for FPGA use. Some convolution-transposed conv sub-parts of t…☆18Feb 25, 2021Updated 5 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆45Sep 26, 2023Updated 2 years ago
- Hardware and Software Co-design implementations☆16Dec 5, 2019Updated 6 years ago
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆16Jan 6, 2023Updated 3 years ago
- ☆14Sep 27, 2022Updated 3 years ago
- This repository contains the details and the code for the MIPS32 ISA based RISC Processor, which is implemented in 5 stage pipelined conf…☆19Apr 26, 2023Updated 3 years ago