AnoushkaTripathi / NASSCOM-VSD-SoC-design-ProgramView external linksLinks
In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transfer Level (RTL) to the Graphical Data System (GDS)
☆18Aug 19, 2024Updated last year
Alternatives and similar repositories for NASSCOM-VSD-SoC-design-Program
Users that are interested in NASSCOM-VSD-SoC-design-Program are comparing it to the libraries listed below
Sorting:
- ☆18Nov 11, 2025Updated 3 months ago
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆35Apr 13, 2024Updated last year
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆15Oct 16, 2021Updated 4 years ago
- This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)☆33Nov 25, 2024Updated last year
- This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…☆11Jul 19, 2022Updated 3 years ago
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆11Aug 26, 2024Updated last year
- ☆13Sep 29, 2024Updated last year
- ☆14Sep 16, 2022Updated 3 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆51Jan 4, 2022Updated 4 years ago
- In this repository, I have shared the codes for designs and testbenches, Elaborated Design and Simulation Output for each block of RISC-V…☆22Aug 28, 2024Updated last year
- Examples of the TCL Scripts for different purposes and for VLSI Physical Design are provided here for your reference☆34Dec 30, 2022Updated 3 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆79Nov 26, 2020Updated 5 years ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆26Apr 29, 2024Updated last year
- Design Verification Engineer interview preparation guide.☆43Jul 20, 2025Updated 6 months ago
- Implementation of RISC-V RV32I☆28Aug 30, 2022Updated 3 years ago
- This repository aims to capture the works done in 5-day workshop of Adavance Physical Design using OpenLANE/SkyWater130. The workshop hel…☆22Jul 5, 2021Updated 4 years ago
- opensource EDA tool flor VLSI design☆36Sep 17, 2023Updated 2 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Apr 18, 2019Updated 6 years ago
- VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.☆31Jul 21, 2025Updated 6 months ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆43Sep 26, 2023Updated 2 years ago
- A SystemVerilog-based simulation and design of a Last Level Cache (LLC) implementing the MESI protocol, featuring Pseudo-LRU replacement,…☆15Nov 24, 2025Updated 2 months ago
- Auto tagging of stack overflow questions. Used dataset: https://www.kaggle.com/stackoverflow/stacksample☆11May 25, 2020Updated 5 years ago
- 5 stage pipeline implementation of RISC-V 32I Processor.☆10Nov 27, 2024Updated last year
- AMD Xilinx University Program Vivado tutorial☆43Feb 13, 2023Updated 3 years ago
- This repository contains the details and the code for the MIPS32 ISA based RISC Processor, which is implemented in 5 stage pipelined conf…☆16Apr 26, 2023Updated 2 years ago
- Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop☆97Mar 6, 2025Updated 11 months ago
- A Simple Flask App to interact with your Machine Translation Model☆13Feb 26, 2020Updated 5 years ago
- ☆14Apr 13, 2025Updated 10 months ago
- Synthesizable SystemVerilog IP-Core of the I2S Receiver☆10Jun 7, 2020Updated 5 years ago
- Tcl examples repository designed primarily for use with the latest version of the Libero® SoC Design Suite.☆11Jul 18, 2024Updated last year
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆15Jan 14, 2021Updated 5 years ago
- This repo Contains the Analog PID Controller designed by using Op-Amp☆16Feb 11, 2024Updated 2 years ago
- Our pipe dream☆13May 9, 2023Updated 2 years ago
- ☆11Nov 17, 2025Updated 3 months ago
- EE4415 Project : AES Verilog☆10Apr 25, 2019Updated 6 years ago
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆16Jan 6, 2023Updated 3 years ago
- ☆41Feb 28, 2022Updated 3 years ago
- ☆13Feb 1, 2025Updated last year
- a mini TPU with floating point arithmetic☆49Dec 22, 2025Updated last month